/*
**************************************************************************
*
* Function : cod_amr_init
* Purpose : Allocates memory and initializes state variables
*
**************************************************************************
*/
int cod_amr_init (cod_amrState **state, Flag dtx)
{
cod_amrState* s;
if (state == (cod_amrState **) NULL){
fprintf(stderr, "cod_amr_init: invalid parameter\n");
return -1;
}
*state = NULL;
/* allocate memory */
if ((s= (cod_amrState *) malloc(sizeof(cod_amrState))) == NULL){
fprintf(stderr, "cod_amr_init: can not malloc state structure\n");
return -1;
}
s->lpcSt = NULL;
s->lspSt = NULL;
s->clLtpSt = NULL;
s->gainQuantSt = NULL;
s->pitchOLWghtSt = NULL;
s->tonStabSt = NULL;
s->vadSt = NULL;
s->dtx_encSt = NULL;
s->dtx = dtx;
/* Init sub states */
if (cl_ltp_init(&s->clLtpSt) ||
lsp_init(&s->lspSt) ||
gainQuant_init(&s->gainQuantSt) ||
p_ol_wgh_init(&s->pitchOLWghtSt) ||
ton_stab_init(&s->tonStabSt) ||
#ifndef VAD2
vad1_init(&s->vadSt) ||
#else
vad2_init(&s->vadSt) ||
#endif
dtx_enc_init(&s->dtx_encSt) ||
lpc_init(&s->lpcSt)) {
cod_amr_exit(&s);
return -1;
}
cod_amr_reset(s);
*state = s;
return 0;
}
static vorbis_look_floor *floor0_look(vorbis_dsp_state *vd,
vorbis_info_floor *i){
int j;
vorbis_info_floor0 *info=(vorbis_info_floor0 *)i;
vorbis_look_floor0 *look=_ogg_calloc(1,sizeof(*look));
look->m=info->order;
look->ln=info->barkmap;
look->vi=info;
if(vd->analysisp)
lpc_init(&look->lpclook,look->ln,look->m);
look->linearmap=_ogg_calloc(2,sizeof(*look->linearmap));
look->lsp_look=_ogg_malloc(look->ln*sizeof(*look->lsp_look));
for(j=0;j<look->ln;j++)
look->lsp_look[j]=2*cos(M_PI/look->ln*j);
return look;
}
static int
pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
{
/*
* Do not allow more than one LPC bridge to be configured.
*/
if (lpc_bridge != NULL)
return (-1);
if (lpc_init() != 0)
return (-1);
/* initialize config space */
pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
lpc_bridge = pi;
return (0);
}
void sb700_after_pci_fixup(void) {
#ifdef ENABLE_SATA
printk_info("sata init\n");
sata_init(_pci_make_tag(0, 0x11, 0));
#endif
printk_info("OHCI0-USB1 init\n");
usb_init(_pci_make_tag(0, 0x12, 0));
printk_info("OHCI1-USB1 init\n");
usb_init(_pci_make_tag(0, 0x12, 1));
#if 1
//printk_info("EHCI-USB1 init\n");
//usb_init2(_pci_make_tag(0, 0x12, 2));
printk_info("OHCI0-USB2 init\n");
usb_init(_pci_make_tag(0, 0x13, 0));
printk_info("OHCI1-USB2 init\n");
usb_init(_pci_make_tag(0, 0x13, 1));
//printk_info("EHCI-USB2 init\n");
//usb_init2(_pci_make_tag(0, 0x13, 2));
printk_info("OHCI0-USB3 init\n");
usb_init(_pci_make_tag(0, 0x14, 5));
#endif
printk_info("lpc init\n");
lpc_init(_pci_make_tag(0, 0x14, 3));
printk_info("ide init\n");
ide_init(_pci_make_tag(0, 0x14, 1));
//vga test
printk_info("pci init\n");
pci_init(_pci_make_tag(0, 0x14, 4));
printk_info("sm init\n");
sm_init(_pci_make_tag(0, 0x14, 0));
#ifdef USE_780E_VGA
printk_info("rs780_internal_gfx_init\n");
internal_gfx_pci_dev_init(_pci_make_tag(0,0,0) , _pci_make_tag(1,0x5,0));
#endif
}
void
lpc_setup(void)
{
lpc_init();
}
/* On boards without a host, this command is used to set up LPC */
static int lpc_command_init(int argc, char **argv)
{
lpc_init();
return EC_SUCCESS;
}
void main(void)
{
int16_t x;
// all generator inits
LPCAnalyzer_init();
init_synth(); // which one? --> klatt rsynth !!!! RENAME!
sp0256_init();
lpc_init();
simpleklatt_init();
sam_init();
sam_newsay(); // TEST!
tms5200_init();
tms5200_newsay();
channelv_init();
tube_init();
// tube_newsay();
BANDS_Init_();
Vocoder_Init(32000.0f);
digitalk_init();
digitalk_newsay(0);
nvp_init();
sample_rate_init();
initbraidworm(); // re_name
initvoicform();
formy=malloc(sizeof(Formlet));
formanty=malloc(sizeof(Formant));
blipper=malloc(sizeof(Blip));
RLPFer=malloc(sizeof(RLPF));
Formlet_init(formy);
Formant_init(formanty);
Blip_init(blipper);
RLPF_init(RLPFer);
NTube_init(&tuber);
// wavetable_init(&wavtable, crowtable_slower, 283); // now last arg as length of table=less than 512
wavetable_init(&wavtable, plaguetable_simplesir, 328); // now last arg as length of table=less than 512
// wavetable_init(&wavtable, table_kahrs000, 160); // now last arg as length of table=less than 512
// addwormsans(&myworm, 10.0f,10.0f,200.0f, 200.0f, wanderworm);
// RavenTube_init();
// newBB=BiQuad_new(LPF, 1.0, 1500, 32000, 0.68); // TEST?
////////
ADC1_Init((uint16_t *)adc_buffer);
Codec_Init(32000);
I2S_Block_Init();
I2S_Block_PlayRec((uint32_t)&tx_buffer, (uint32_t)&rx_buffer, BUFF_LEN);
// Audio_Init(); not needed
// tube_init();
// tube_newsay();
// initializeSynthesizer();
// synthesize();
// lpc_newsay(1);
// SAMINIT();
// test audio fill
/* for (x=0;x<32768;x++){
audio_buffer[x]=tube_get_sample();
}*/
// int writepos=run_holmes(writepos);
/* for (x=0;x<32767;x++){
audio_buffer[x]=tube_get_sample();
}
*/
while(1)
{
// testing changing test_elm
// u8 axis=adc_buffer[SELX]>>8; // 16*3=48
// change element, change length? leave stress as is 0
// test_elm[axis*3]=phoneme_prob_remap[adc_buffer[SELY]>>6]; // how many phonemes?=64
// test_elm[(axis*3)+1]=(adc_buffer[SELZ]>>7)+1; // length say max 32
// oldmode=mode;
// mode=adc_buffer[MODE]>>7; // 12 bits to say 32 modes (5 bits)
// mode=10; // TESTING
// if(lpc_busy() == 0) lpc_newsay(adc_buffer[SELX]>>6);
// if(lpc_busy() != 0) lpc_running(); // so just writes once otherwise gets messy...
// if there is a change in mode do something?
// if (oldmode!=mode){
// maintrigger=1;
// }
/* if (maintrigger==1) {writepos=0;trigger=1;} // STRIP_OUT
switch(mode){
case 0:// rsynth/klatt-single phoneme
if (trigger==1){
trigger=0;
u8 phonemm=phoneme_prob_remap[(adc_buffer[SELX]>>6)]; // 7bits=128 %69//6=64
pair xx=klatt_phoneme(writepos,phonemm);
generated=xx.generated;
writepos=xx.writepos;
}
break;
case 1: // rsynth/klatt-chain of phonemes
writepos=run_holmes(writepos);
break;
case 2: // vosim free running
writepos=runVOSIM_SC(writepos);
break;
case 3: // VOSIMondemand
if (trigger==1){
trigger=0;
float freqwency = (float)((adc_buffer[SELX])+100);//1500.0f;
float cycles = (float)((adc_buffer[SELY]>>4)+2);
float decay = ((float)(adc_buffer[SELZ])/4096.0f); // TODO as SELZ!
pair xx=demandVOSIM_SC(writepos,freqwency,cycles,decay);
generated=xx.generated;
writepos=xx.writepos;
}
break;
case 9: // SAM full. no writepos though and just a simple proof here
if (trigger==0){
SAMMain();
trigger=1;
}
break;
case 10:
if(lpc_busy() == 0) lpc_newsay(adc_buffer[SELX]>>6);
if(lpc_busy() != 0) lpc_running(); // so just writes once otherwise gets messy...
break;
case 19: // parwave/simpleklatt
dosimpleklatt();
break;
} // cases
// now readpos is back to one now that we have written something
if (maintrigger==1) {
readpos=0;
maintrigger=0;
}
*/
}
}
