void genadd(void) { #ifdef INTERPRET_ADD gencallinterp((unsigned int)cached_interpreter_table.ADD, 0); #else int rs = allocate_register((unsigned int *)g_dev.r4300.recomp.dst->f.r.rs); int rt = allocate_register((unsigned int *)g_dev.r4300.recomp.dst->f.r.rt); int rd = allocate_register_w((unsigned int *)g_dev.r4300.recomp.dst->f.r.rd); if (rt != rd && rs != rd) { mov_reg32_reg32(rd, rs); add_reg32_reg32(rd, rt); } else { int temp = lru_register(); free_register(temp); mov_reg32_reg32(temp, rs); add_reg32_reg32(temp, rt); mov_reg32_reg32(rd, temp); } #endif }
int allocate_64_register2_w(unsigned int *addr) { int reg1, reg2, i; // is it already cached as a 32 bits value ? for (i=0; i<8; i++) { if (last_access[i] != NULL && reg_content[i] == addr) { if (r64[i] == -1) { allocate_register_w(addr); reg2 = lru_register(); if (last_access[reg2]) free_register(reg2); else { while (free_since[reg2] <= dst) { free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL; free_since[reg2]++; } } r64[i] = reg2; r64[reg2] = i; last_access[reg2] = dst; reg_content[reg2] = addr+1; dirty[reg2] = 1; mov_reg32_reg32(reg2, i); sar_reg32_imm8(reg2, 31); return reg2; } else { last_access[i] = dst; last_access[r64[i]] = dst; dirty[i] = dirty[r64[i]] = 1; return r64[i]; } } } reg1 = allocate_register_w(addr); reg2 = lru_register(); if (last_access[reg2]) free_register(reg2); else { while (free_since[reg2] <= dst) { free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL; free_since[reg2]++; } } r64[reg1] = reg2; r64[reg2] = reg1; last_access[reg2] = dst; reg_content[reg2] = addr+1; dirty[reg2] = 1; return reg2; }
int allocate_64_register2_w(unsigned int *addr) { int reg1, reg2, i; // is it already cached as a 32 bits value ? for (i=0; i<8; i++) { if (g_dev.r4300.regcache_state.last_access[i] != NULL && g_dev.r4300.regcache_state.reg_content[i] == addr) { if (g_dev.r4300.regcache_state.r64[i] == -1) { allocate_register_w(addr); reg2 = lru_register(); if (g_dev.r4300.regcache_state.last_access[reg2]) free_register(reg2); else { while (g_dev.r4300.regcache_state.free_since[reg2] <= g_dev.r4300.recomp.dst) { g_dev.r4300.regcache_state.free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL; g_dev.r4300.regcache_state.free_since[reg2]++; } } g_dev.r4300.regcache_state.r64[i] = reg2; g_dev.r4300.regcache_state.r64[reg2] = i; g_dev.r4300.regcache_state.last_access[reg2] = g_dev.r4300.recomp.dst; g_dev.r4300.regcache_state.reg_content[reg2] = addr+1; g_dev.r4300.regcache_state.dirty[reg2] = 1; mov_reg32_reg32(reg2, i); sar_reg32_imm8(reg2, 31); return reg2; } else { g_dev.r4300.regcache_state.last_access[i] = g_dev.r4300.recomp.dst; g_dev.r4300.regcache_state.last_access[g_dev.r4300.regcache_state.r64[i]] = g_dev.r4300.recomp.dst; g_dev.r4300.regcache_state.dirty[i] = g_dev.r4300.regcache_state.dirty[g_dev.r4300.regcache_state.r64[i]] = 1; return g_dev.r4300.regcache_state.r64[i]; } } } reg1 = allocate_register_w(addr); reg2 = lru_register(); if (g_dev.r4300.regcache_state.last_access[reg2]) free_register(reg2); else { while (g_dev.r4300.regcache_state.free_since[reg2] <= g_dev.r4300.recomp.dst) { g_dev.r4300.regcache_state.free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL; g_dev.r4300.regcache_state.free_since[reg2]++; } } g_dev.r4300.regcache_state.r64[reg1] = reg2; g_dev.r4300.regcache_state.r64[reg2] = reg1; g_dev.r4300.regcache_state.last_access[reg2] = g_dev.r4300.recomp.dst; g_dev.r4300.regcache_state.reg_content[reg2] = addr+1; g_dev.r4300.regcache_state.dirty[reg2] = 1; return reg2; }
int allocate_64_register2_w(usf_state_t * state, unsigned int *addr) { int reg1, reg2, i; // is it already cached as a 32 bits value ? for (i=0; i<8; i++) { if (state->last_access[i] != NULL && state->reg_content[i] == addr) { if (state->r64[i] == -1) { allocate_register_w(state, addr); reg2 = lru_register(state); if (state->last_access[reg2]) free_register(state, reg2); else { while (state->free_since[reg2] <= state->dst) { state->free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL; state->free_since[reg2]++; } } state->r64[i] = reg2; state->r64[reg2] = i; state->last_access[reg2] = state->dst; state->reg_content[reg2] = addr+1; state->dirty[reg2] = 1; mov_reg32_reg32(state, reg2, i); sar_reg32_imm8(state, reg2, 31); return reg2; } else { state->last_access[i] = state->dst; state->last_access[state->r64[i]] = state->dst; state->dirty[i] = state->dirty[state->r64[i]] = 1; return state->r64[i]; } } } reg1 = allocate_register_w(state, addr); reg2 = lru_register(state); if (state->last_access[reg2]) free_register(state, reg2); else { while (state->free_since[reg2] <= state->dst) { state->free_since[reg2]->reg_cache_infos.needed_registers[reg2] = NULL; state->free_since[reg2]++; } } state->r64[reg1] = reg2; state->r64[reg2] = reg1; state->last_access[reg2] = state->dst; state->reg_content[reg2] = addr+1; state->dirty[reg2] = 1; return reg2; }