void __init arch_init_irq(void) { /* hardware initialization */ nile4_irq_setup(); m1543_irq_setup(); /* controller setup */ init_i8259_irqs(); vrc5476_irq_init(VRC5476_IRQ_BASE); mips_cpu_irq_init(CPU_IRQ_BASE); /* setup cascade interrupts */ setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade); setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade); /* setup error interrupts for debugging */ setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error); /* setup the grandpa intr vector */ set_except_vector(0, ddb5476_handle_int); }
void __init ddb_irq_setup(void) { #ifdef CONFIG_REMOTE_DEBUG if (remote_debug) set_debug_traps(); breakpoint(); /* you may move this line to whereever you want :-) */ #endif request_region(0x20, 0x20, "pic1"); request_region(0xa0, 0x20, "pic2"); i8259_setup_irq(2, &irq2); nile4_irq_setup(); m1543_irq_setup(); set_except_vector(0, ddbIRQ); }
void __init arch_init_irq(void) { /* setup cascade interrupts */ setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade); setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade); set_except_vector(0, ddbIRQ); nile4_irq_setup(NILE4_IRQ_BASE); m1543_irq_setup(); init_i8259_irqs(); printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE); mips_cpu_irq_init(CPU_IRQ_BASE); printk("enabling 8259 cascade\n"); ddb5074_led_hex(0); /* Enable the interrupt cascade */ nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE); }