static int m6502_execute(int cycles)
{
m6502_ICount = cycles;
change_pc(PCD);
do
{
UINT8 op;
PPC = PCD;
CALL_MAME_DEBUG;
#if 1
/* if an irq is pending, take it now */
if( m6502.pending_irq )
m6502_take_irq();
op = RDOP();
(*m6502.insn[op])();
#else
/* thought as irq request while executing sei */
/* sei sets I flag on the stack*/
op = RDOP();
/* if an irq is pending, take it now */
if( m6502.pending_irq && (op == 0x78) )
m6502_take_irq();
(*m6502.insn[op])();
#endif
/* check if the I flag was just reset (interrupts enabled) */
if( m6502.after_cli )
{
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
m6502.after_cli = 0;
if (m6502.irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
m6502.pending_irq = 1;
}
else
{
LOG((": irq line is clear\n"));
}
}
else
if( m6502.pending_irq )
m6502_take_irq();
} while (m6502_ICount > 0);
return cycles - m6502_ICount;
}
static CPU_EXECUTE( m6502 )
{
m6502_Regs *cpustate = get_safe_token(device);
do
{
UINT8 op;
PPC = PCD;
debugger_instruction_hook(device, PCD);
/* if an irq is pending, take it now */
if( cpustate->pending_irq )
m6502_take_irq(cpustate);
op = RDOP();
(*cpustate->insn[op])(cpustate);
/* check if the I flag was just reset (interrupts enabled) */
if( cpustate->after_cli )
{
LOG(("M6502 '%s' after_cli was >0", cpustate->device->tag()));
cpustate->after_cli = 0;
if (cpustate->irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
cpustate->pending_irq = 1;
}
else
{
LOG((": irq line is clear\n"));
}
}
else {
if ( cpustate->pending_irq == 2 ) {
if ( cpustate->int_occured - cpustate->icount > 1 ) {
cpustate->pending_irq = 1;
}
}
if( cpustate->pending_irq == 1 )
m6502_take_irq(cpustate);
if ( cpustate->pending_irq == 2 ) {
cpustate->pending_irq = 1;
}
}
} while (cpustate->icount > 0);
}
/* The N2A03 is integrally tied to its PSG (they're on the same die).
Bit 7 of address $4011 (the PSG's DPCM control register), when set,
causes an IRQ to be generated. This function allows the IRQ to be called
from the PSG core when such an occasion arises. */
void n2a03_irq(void)
{
m6502_take_irq();
}
/* The N2A03 is integrally tied to its PSG (they're on the same die).
Bit 7 of address $4011 (the PSG's DPCM control register), when set,
causes an IRQ to be generated. This function allows the IRQ to be called
from the PSG core when such an occasion arises. */
void n2a03_irq(device_t *device)
{
m6502_Regs *cpustate = get_safe_token(device);
m6502_take_irq(cpustate);
}
