void bsp_start( void )
{
/*
* Invalidate the cache and disable it
*/
m68k_set_acr0(0);
m68k_set_acr1(0);
m68k_set_cacr(MCF5XXX_CACR_CINV);
/*
* Cache SDRAM and FLASH
*/
m68k_set_acr0(
MCF5XXX_ACR_AB(SDRAM_BASE) |
MCF5XXX_ACR_AM(SDRAM_SIZE-1) |
MCF5XXX_ACR_EN |
MCF5XXX_ACR_BWE |
MCF5XXX_ACR_SM_IGNORE
);
/*
* Enable the cache
*/
mcf5xxx_initialize_cacr(
MCF5XXX_CACR_CENB |
MCF5XXX_CACR_DBWE |
MCF5XXX_CACR_DCM
);
}
void bsp_cacr_set_flags( uint32_t flags)
{
rtems_interrupt_level level;
rtems_interrupt_disable( level);
_CPU_cacr_shadow |= flags;
m68k_set_cacr( _CPU_cacr_shadow);
rtems_interrupt_enable( level);
}
void _CPU_cache_enable_data(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
cacr_mode &= ~MCF5XXX_CACR_DISD;
m68k_set_cacr(cacr_mode);
rtems_interrupt_enable(level);
}
void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
cacr_mode |= MCF5XXX_CACR_DIDI;
m68k_set_cacr(cacr_mode);
rtems_interrupt_enable(level);
}
void bsp_cacr_set_self_clear_flags( uint32_t flags)
{
rtems_interrupt_level level;
uint32_t cacr = 0;
rtems_interrupt_disable( level);
cacr = _CPU_cacr_shadow | flags;
m68k_set_cacr( cacr);
rtems_interrupt_enable( level);
}
void _CPU_cache_disable_instruction(void)
{
rtems_interrupt_level level;
rtems_interrupt_disable(level);
if((cacr_mode & MCF_CACR_CENB))
{
cacr_mode &= ~MCF_CACR_CENB;
m68k_set_cacr(cacr_mode);
}
rtems_interrupt_enable(level);
}
/*
* bsp_start
*
* This routine does the bulk of the system initialisation.
*/
void bsp_start( void )
{
/*
* Invalidate the cache and disable it
*/
m68k_set_acr0(0);
m68k_set_acr1(0);
m68k_set_cacr(MCF5XXX_CACR_CINV);
/*
* Cache SDRAM
*/
m68k_set_acr0(MCF5XXX_ACR_AB((uintptr_t)RamBase) |
MCF5XXX_ACR_AM((uintptr_t)RamSize-1) |
MCF5XXX_ACR_EN |
MCF5XXX_ACR_BWE |
MCF5XXX_ACR_SM_IGNORE);
/*
* Enable the cache
*/
m68k_set_cacr(cacr_mode);
}
/*
* bsp_start
*
* This routine does the bulk of the system initialisation.
*/
void bsp_start( void )
{
/* Initialize CACR shadow register */
_CPU_cacr_shadow = BSP_CACR_INIT;
/*
* Load the shadow variable of CACR with initial mode and write it to the
* CACR. Interrupts are still disabled, so there is no need for surrounding
* rtems_interrupt_enable() / rtems_interrupt_disable().
*/
m68k_set_cacr( _CPU_cacr_shadow);
/*
* do mapping of acr's and/or mmu
*/
acr_mmu_mapping();
}
/* init5272 --
* Initialize MCF5272 on-chip modules
*
* PARAMETERS:
* none
*
* RETURNS:
* none
*/
void
init5272(void)
{
extern void clear_bss(void);
extern void start_csb360(void);
/* Invalidate the cache - WARNING: It won't complete for 64 clocks */
m68k_set_cacr(MCF5272_CACR_CINV);
/* Set Module Base Address register */
m68k_set_mbar((BSP_MBAR & MCF5272_MBAR_BA) | MCF5272_MBAR_V);
/* Set RAM Base Address register */
m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
/* Set System Control Register:
* Enet has highest priority, 16384 bus cycles before timeout
*/
g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
/* System Protection Register:
* Enable Hardware watchdog timer.
*/
g_sim_regs->spr = MCF5272_SPR_HWTEN;
/* Clear and mask all interrupts */
g_intctrl_regs->icr1 = 0x88888888;
g_intctrl_regs->icr2 = 0x88888888;
g_intctrl_regs->icr3 = 0x88888888;
g_intctrl_regs->icr4 = 0x88880000;
/* Copy the interrupt vector table to SRAM */
{
extern void INTERRUPT_VECTOR();
uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
uint32_t *intvec = (uint32_t *)BSP_RAMBAR;
register int i;
for (i = 0; i < 256; i++)
{
*(intvec++) = *(inttab++);
}
}
m68k_set_vbr(BSP_RAMBAR);
/*
* Setup ACRs so that if cache turned on, periphal accesses
* are not messed up. (Non-cacheable, serialized)
*/
m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM) |
MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM) |
MCF5272_ACR_EN |
MCF5272_ACR_SM_ANY);
/*
m68k_set_acr1 (MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) |
MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) |
MCF5206E_ACR_EN |
MCF5206E_ACR_SM_ANY);
*/
/* Enable the caches */
m68k_set_cacr(MCF5272_CACR_CENB |
MCF5272_CACR_DCM); /* Default is not cached */
/*
* Copy data, clear BSS, switch stacks and call boot_card()
*/
/*
CopyDataClearBSSAndStart(BSP_MEM_SIZE_ESRAM - 0x400);
*/
clear_bss();
start_csb360();
}
void _CPU_cache_invalidate_entire_instruction(void)
{
m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
}
void _CPU_cache_invalidate_entire_data(void)
{
m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
}
