static fp_reg READ_EA_FPE(m68ki_cpu_core *m68k, int ea) { fp_reg r; int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); // TODO: convert to extended floating-point! switch (mode) { case 3: // (An)+ { UINT32 d1,d2,d3; UINT32 ea = REG_A[reg]; REG_A[reg] += 12; d1 = m68ki_read_32(m68k, ea+0); d2 = m68ki_read_32(m68k, ea+4); d3 = m68ki_read_32(m68k, ea+8); r.i = (UINT64)(d1) << 32 | (UINT64)(d2); break; } default: fatalerror("MC68040: READ_EA_FPE: unhandled mode %d, reg %d, at %08X\n", mode, reg, REG_PC); } return r; }
static void fmove_fpcr(m68ki_cpu_core *m68k, UINT16 w2) { int ea = m68k->ir & 0x3f; int dir = (w2 >> 13) & 0x1; int regsel = (w2 >> 10) & 0x7; int mode = (ea >> 3) & 0x7; if ((mode == 5) || (mode == 6)) { UINT32 address = 0xffffffff; // force a bus error if this doesn't get assigned if (mode == 5) { address = EA_AY_DI_32(m68k); } else if (mode == 6) { address = EA_AY_IX_32(m68k); } if (dir) // From system control reg to <ea> { if (regsel & 4) { m68ki_write_32(m68k, address, REG_FPCR(m68k)); address += 4; } if (regsel & 2) { m68ki_write_32(m68k, address, REG_FPSR(m68k)); address += 4; } if (regsel & 1) { m68ki_write_32(m68k, address, REG_FPIAR(m68k)); address += 4; } } else // From <ea> to system control reg { if (regsel & 4) { REG_FPCR(m68k) = m68ki_read_32(m68k, address); address += 4; } if (regsel & 2) { REG_FPSR(m68k) = m68ki_read_32(m68k, address); address += 4; } if (regsel & 1) { REG_FPIAR(m68k) = m68ki_read_32(m68k, address); address += 4; } } } else { if (dir) // From system control reg to <ea> { if (regsel & 4) WRITE_EA_32(m68k, ea, REG_FPCR(m68k)); if (regsel & 2) WRITE_EA_32(m68k, ea, REG_FPSR(m68k)); if (regsel & 1) WRITE_EA_32(m68k, ea, REG_FPIAR(m68k)); } else // From <ea> to system control reg { if (regsel & 4) REG_FPCR(m68k) = READ_EA_32(m68k, ea); if (regsel & 2) REG_FPSR(m68k) = READ_EA_32(m68k, ea); if (regsel & 1) REG_FPIAR(m68k) = READ_EA_32(m68k, ea); } } m68k->remaining_cycles -= 10; }
INLINE floatx80 load_pack_float80(m68000_base_device *m68k, UINT32 ea) { UINT32 dw1, dw2, dw3; floatx80 result; double tmp; char str[128], *ch; dw1 = m68ki_read_32(m68k, ea); dw2 = m68ki_read_32(m68k, ea+4); dw3 = m68ki_read_32(m68k, ea+8); ch = &str[0]; if (dw1 & 0x80000000) // mantissa sign { *ch++ = '-'; } *ch++ = (char)((dw1 & 0xf) + '0'); *ch++ = '.'; *ch++ = (char)(((dw2 >> 28) & 0xf) + '0'); *ch++ = (char)(((dw2 >> 24) & 0xf) + '0'); *ch++ = (char)(((dw2 >> 20) & 0xf) + '0'); *ch++ = (char)(((dw2 >> 16) & 0xf) + '0'); *ch++ = (char)(((dw2 >> 12) & 0xf) + '0'); *ch++ = (char)(((dw2 >> 8) & 0xf) + '0'); *ch++ = (char)(((dw2 >> 4) & 0xf) + '0'); *ch++ = (char)(((dw2 >> 0) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 28) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 24) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 20) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 16) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 12) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 8) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 4) & 0xf) + '0'); *ch++ = (char)(((dw3 >> 0) & 0xf) + '0'); *ch++ = 'E'; if (dw1 & 0x40000000) // exponent sign { *ch++ = '-'; } *ch++ = (char)(((dw1 >> 24) & 0xf) + '0'); *ch++ = (char)(((dw1 >> 20) & 0xf) + '0'); *ch++ = (char)(((dw1 >> 16) & 0xf) + '0'); *ch = '\0'; sscanf(str, "%le", &tmp); result = double_to_fx80(tmp); return result; }
INLINE floatx80 load_extended_float80(m68000_base_device *m68k, UINT32 ea) { UINT32 d1,d2; UINT16 d3; floatx80 fp; d3 = m68ki_read_16(m68k, ea); d1 = m68ki_read_32(m68k, ea+4); d2 = m68ki_read_32(m68k, ea+8); fp.high = d3; fp.low = ((UINT64)d1<<32) | (d2 & 0xffffffff); return fp; }
static UINT64 READ_EA_64(m68ki_cpu_core *m68k, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); UINT32 h1, h2; switch (mode) { case 2: // (An) { UINT32 ea = REG_A[reg]; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 3: // (An)+ { UINT32 ea = REG_A[reg]; REG_A[reg] += 8; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 7: { switch (reg) { case 4: // #<data> { h1 = OPER_I_32(m68k); h2 = OPER_I_32(m68k); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } default: fatalerror("MC68040: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } break; } default: fatalerror("MC68040: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } return 0; }
static UINT32 READ_EA_32(m68ki_cpu_core *m68k, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); switch (mode) { case 0: // Dn { return REG_D[reg]; } case 2: // (An) { UINT32 ea = REG_A[reg]; return m68ki_read_32(m68k, ea); } case 3: // (An)+ { UINT32 ea = EA_AY_PI_32(m68k); return m68ki_read_32(m68k, ea); } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); return m68ki_read_32(m68k, ea); } case 6: // (An) + (Xn) + d8 { UINT32 ea = EA_AY_IX_32(m68k); return m68ki_read_32(m68k, ea); } case 7: { switch (reg) { case 1: // (xxx).L { UINT32 d1 = OPER_I_16(m68k); UINT32 d2 = OPER_I_16(m68k); UINT32 ea = (d1 << 16) | d2; return m68ki_read_32(m68k, ea); } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); return m68ki_read_32(m68k, ea); } case 4: // #<data> { return OPER_I_32(m68k); } default: fatalerror("MC68040: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } break; } default: fatalerror("MC68040: READ_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC); } return 0; }
static UINT64 READ_EA_64(m68000_base_device *m68k, int ea) { int mode = (ea >> 3) & 0x7; int reg = (ea & 0x7); UINT32 h1, h2; switch (mode) { case 2: // (An) { UINT32 ea = REG_A(m68k)[reg]; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 3: // (An)+ { UINT32 ea = REG_A(m68k)[reg]; REG_A(m68k)[reg] += 8; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 4: // -(An) { UINT32 ea = REG_A(m68k)[reg]-8; REG_A(m68k)[reg] -= 8; h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 5: // (d16, An) { UINT32 ea = EA_AY_DI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 6: // (An) + (Xn) + d8 { UINT32 ea = EA_AY_IX_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 7: { switch (reg) { case 1: // (xxx).L { UINT32 d1 = OPER_I_16(m68k); UINT32 d2 = OPER_I_16(m68k); UINT32 ea = (d1 << 16) | d2; return (UINT64)(m68ki_read_32(m68k, ea)) << 32 | (UINT64)(m68ki_read_32(m68k, ea+4)); } case 3: // (PC) + (Xn) + d8 { UINT32 ea = EA_PCIX_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 4: // #<data> { h1 = OPER_I_32(m68k); h2 = OPER_I_32(m68k); return (UINT64)(h1) << 32 | (UINT64)(h2); } case 2: // (d16, PC) { UINT32 ea = EA_PCDI_32(m68k); h1 = m68ki_read_32(m68k, ea+0); h2 = m68ki_read_32(m68k, ea+4); return (UINT64)(h1) << 32 | (UINT64)(h2); } default: fatalerror("M68kFPU: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k)); } break; } default: fatalerror("M68kFPU: READ_EA_64: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k)); } return 0; }
static void fmove_fpcr(m68000_base_device *m68k, UINT16 w2) { int ea = m68k->ir & 0x3f; int dir = (w2 >> 13) & 0x1; int regsel = (w2 >> 10) & 0x7; int mode = (ea >> 3) & 0x7; if ((mode == 5) || (mode == 6)) { UINT32 address = 0xffffffff; // force a bus error if this doesn't get assigned if (mode == 5) { address = EA_AY_DI_32(m68k); } else if (mode == 6) { address = EA_AY_IX_32(m68k); } if (dir) // From system control reg to <ea> { if (regsel & 4) { m68ki_write_32(m68k, address, REG_FPCR(m68k)); address += 4; } if (regsel & 2) { m68ki_write_32(m68k, address, REG_FPSR(m68k)); address += 4; } if (regsel & 1) { m68ki_write_32(m68k, address, REG_FPIAR(m68k)); address += 4; } } else // From <ea> to system control reg { if (regsel & 4) { REG_FPCR(m68k) = m68ki_read_32(m68k, address); address += 4; } if (regsel & 2) { REG_FPSR(m68k) = m68ki_read_32(m68k, address); address += 4; } if (regsel & 1) { REG_FPIAR(m68k) = m68ki_read_32(m68k, address); address += 4; } } } else { if (dir) // From system control reg to <ea> { if (regsel & 4) WRITE_EA_32(m68k, ea, REG_FPCR(m68k)); if (regsel & 2) WRITE_EA_32(m68k, ea, REG_FPSR(m68k)); if (regsel & 1) WRITE_EA_32(m68k, ea, REG_FPIAR(m68k)); } else // From <ea> to system control reg { if (regsel & 4) REG_FPCR(m68k) = READ_EA_32(m68k, ea); if (regsel & 2) REG_FPSR(m68k) = READ_EA_32(m68k, ea); if (regsel & 1) REG_FPIAR(m68k) = READ_EA_32(m68k, ea); } } #if 0 // FIXME: (2011-12-18 ost) // rounding_mode and rounding_precision of softfloat.c should be set according to current fpcr // but: with this code on Apollo the following programs in /systest/fptest will fail: // 1. Single Precision Whetstone will return wrong results never the less // 2. Vector Test will fault with 00040004: reference to illegal address if ((regsel & 4) && dir == 0) { int rnd = (REG_FPCR(m68k) >> 4) & 3; int prec = (REG_FPCR(m68k) >> 6) & 3; logerror("m68k_fpsp:fmove_fpcr fpcr=%04x prec=%d rnd=%d\n", REG_FPCR(m68k), prec, rnd); #ifdef FLOATX80 switch (prec) { case 0: // Extend (X) floatx80_rounding_precision = 80; break; case 1: // Single (S) floatx80_rounding_precision = 32; break; case 2: // Double (D) floatx80_rounding_precision = 64; break; case 3: // Undefined floatx80_rounding_precision = 80; break; } #endif switch (rnd) { case 0: // To Nearest (RN) float_rounding_mode = float_round_nearest_even; break; case 1: // To Zero (RZ) float_rounding_mode = float_round_to_zero; break; case 2: // To Minus Infinitiy (RM) float_rounding_mode = float_round_down; break; case 3: // To Plus Infinitiy (RP) float_rounding_mode = float_round_up; break; } }