void malifix_init(void)
{
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
if (!mali_meson_is_revb())
return;
if ((mali_mm1_regs) && (mali_mm2_regs)) return;
mali_mmu_int_process_state[0] = 0;
mali_mmu_int_process_state[1] = 0;
/* set up Timer C as a 1uS one-shot timer */
aml_clr_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(1<<14)|(3<<4));
aml_set_reg32_mask(P_ISA_TIMER_MUX, (1<<18)|(0<<14)|(0<<4));
setup_timer(&timer, timer_callback, 0);
mali_mm1_regs = (ulong *)ioremap_nocache(MALI_MM1_REG_ADDR, MALI_MM_REG_SIZE);
if (mali_mm1_regs)
printk("Mali pp1 MMU register mapped at %p...\n", mali_mm1_regs);
mali_mm2_regs = (ulong *)ioremap_nocache(MALI_MM2_REG_ADDR, MALI_MM_REG_SIZE);
if (mali_mm2_regs)
printk("Mali pp2 MMU register mapped at %p...\n", mali_mm2_regs);
if ((mali_mm1_regs != NULL) && (mali_mm2_regs != NULL))
mod_timer(&timer, jiffies + HZ/100);
#endif
}
void malifix_exit(void)
{
if (!mali_meson_is_revb())
return;
del_timer(&timer);
if (mali_mm1_regs != NULL)
iounmap(mali_mm1_regs);
mali_mm1_regs = NULL;
if (mali_mm2_regs != NULL)
iounmap(mali_mm2_regs);
mali_mm2_regs = NULL;
return;
}
void malifix_exit(void)
{
#if MESON_CPU_TYPE == MESON_CPU_TYPE_MESON6
if (!mali_meson_is_revb())
return;
del_timer(&timer);
if (mali_mm1_regs != NULL)
iounmap(mali_mm1_regs);
mali_mm1_regs = NULL;
if (mali_mm2_regs != NULL)
iounmap(mali_mm2_regs);
mali_mm2_regs = NULL;
#endif
return;
}
static void mali_meson_poweron(int first_poweron)
{
unsigned long flags;
u32 p, p_aligned;
dma_addr_t p_phy;
int i;
unsigned int_mask;
if(!first_poweron) {
if ((last_power_mode != -1) && (last_power_mode != MALI_POWER_MODE_DEEP_SLEEP)) {
MALI_DEBUG_PRINT(3, ("Maybe your system not deep sleep now.......\n"));
//printk("Maybe your system not deep sleep now.......\n");
return;
}
}
MALI_DEBUG_PRINT(2, ("mali_meson_poweron: Mali APB bus accessing\n"));
if (READ_MALI_REG(MALI_PP_PP_VERSION) != MALI_PP_PP_VERSION_MAGIC) {
MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali APB bus access failed\n"));
//printk("mali_meson_poweron: Mali APB bus access failed.");
return;
}
MALI_DEBUG_PRINT(2, ("..........accessing done.\n"));
if (READ_MALI_REG(MALI_MMU_DTE_ADDR) != 0) {
MALI_DEBUG_PRINT(3, ("mali_meson_poweron: Mali is not really powered off\n"));
//printk("mali_meson_poweron: Mali is not really powered off.");
return;
}
p = (u32)kcalloc(4096 * 4, 1, GFP_KERNEL);
if (!p) {
printk("mali_meson_poweron: NOMEM in meson_poweron\n");
return;
}
p_aligned = __ALIGN_MASK(p, 4096);
/* DTE */
*(u32 *)(p_aligned) = (virt_to_phys((void *)p_aligned) + OFFSET_MMU_PTE) | MMU_FLAG_DTE_PRESENT;
/* PTE */
for (i=0; i<1024; i++) {
*(u32 *)(p_aligned + OFFSET_MMU_PTE + i*4) =
(virt_to_phys((void *)p_aligned) + OFFSET_MMU_VIRTUAL_ZERO + 4096 * i) |
MMU_FLAG_PTE_PAGE_PRESENT |
MMU_FLAG_PTE_RD_PERMISSION;
}
/* command & data */
memcpy((void *)(p_aligned + OFFSET_MMU_VIRTUAL_ZERO), poweron_data, 4096);
p_phy = dma_map_single(NULL, (void *)p_aligned, 4096 * 3, DMA_TO_DEVICE);
/* Set up Mali GP MMU */
WRITE_MALI_REG(MALI_MMU_DTE_ADDR, p_phy);
WRITE_MALI_REG(MALI_MMU_CMD, 0);
if ((READ_MALI_REG(MALI_MMU_STATUS) & 1) != 1)
printk("mali_meson_poweron: MMU enabling failed.\n");
/* Set up Mali command registers */
WRITE_MALI_REG(MALI_APB_GP_VSCL_START, 0);
WRITE_MALI_REG(MALI_APB_GP_VSCL_END, 0x38);
spin_lock_irqsave(&lock, flags);
int_mask = READ_MALI_REG(MALI_APB_GP_INT_MASK);
WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
WRITE_MALI_REG(MALI_APB_GP_INT_MASK, 0);
/* Start GP */
WRITE_MALI_REG(MALI_APB_GP_CMD, 1);
for (i = 0; i<100; i++)
udelay(500);
/* check Mali GP interrupt */
if (READ_MALI_REG(MALI_APB_GP_INT_RAWSTAT) & 0x707bff)
printk("mali_meson_poweron: Interrupt received.\n");
else
printk("mali_meson_poweron: No interrupt received.\n");
/* force reset GP */
WRITE_MALI_REG(MALI_APB_GP_CMD, 1 << 5);
/* stop MMU paging and reset */
WRITE_MALI_REG(MALI_MMU_CMD, 1);
WRITE_MALI_REG(MALI_MMU_CMD, 6);
for (i = 0; i<100; i++)
udelay(500);
WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x3ff);
WRITE_MALI_REG(MALI_MMU_INT_CLEAR, INT_ALL);
WRITE_MALI_REG(MALI_MMU_INT_MASK, 0);
WRITE_MALI_REG(MALI_APB_GP_INT_CLEAR, 0x707bff);
WRITE_MALI_REG(MALI_APB_GP_INT_MASK, int_mask);
spin_unlock_irqrestore(&lock, flags);
dma_unmap_single(NULL, p_phy, 4096 * 3, DMA_TO_DEVICE);
kfree((void *)p);
/* Mali revision detection */
if (last_power_mode == -1)
mali_revb_flag = mali_meson_is_revb();
}
