struct komeda_dev_funcs *
d71_identify(u32 __iomem *reg_base, struct komeda_chip_info *chip)
{
chip->arch_id = malidp_read32(reg_base, GLB_ARCH_ID);
chip->core_id = malidp_read32(reg_base, GLB_CORE_ID);
chip->core_info = malidp_read32(reg_base, GLB_CORE_INFO);
return &d71_chip_funcs;
}
static void get_values_from_reg(void __iomem *reg, u32 offset,
u32 count, u32 *val)
{
u32 i, addr;
for (i = 0; i < count; i++) {
addr = offset + (i << 2);
/* 0xA4 is WO register */
if (addr != 0xA4)
val[i] = malidp_read32(reg, addr);
else
val[i] = 0xDEADDEAD;
}
}
static int d71_layer_init(struct d71_dev *d71,
struct block_header *blk, u32 __iomem *reg)
{
struct komeda_component *c;
struct komeda_layer *layer;
u32 pipe_id, layer_id, layer_info;
get_resources_id(blk->block_info, &pipe_id, &layer_id);
c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*layer),
layer_id,
BLOCK_INFO_INPUT_ID(blk->block_info),
&d71_layer_funcs, 0,
get_valid_inputs(blk),
1, reg, "LPU%d_LAYER%d", pipe_id, layer_id);
if (IS_ERR(c)) {
DRM_ERROR("Failed to add layer component\n");
return PTR_ERR(c);
}
layer = to_layer(c);
layer_info = malidp_read32(reg, LAYER_INFO);
if (layer_info & L_INFO_RF)
layer->layer_type = KOMEDA_FMT_RICH_LAYER;
else
layer->layer_type = KOMEDA_FMT_SIMPLE_LAYER;
set_range(&layer->hsize_in, 4, d71->max_line_size);
set_range(&layer->vsize_in, 4, d71->max_vsize);
malidp_write32(reg, LAYER_PALPHA, D71_PALPHA_DEF_MAP);
layer->supported_rots = DRM_MODE_ROTATE_MASK | DRM_MODE_REFLECT_MASK;
return 0;
}
