// Configure pin as input floating static void stm32_gpio_deactivate(void *driver_data, uint8_t pin) { uint32_t cfgset; int ret; lldbg("%s: pin=%hhu\n", __func__, pin); ret = map_pin_nr_to_cfgset(pin, &cfgset); if (ret) { lldbg("%s: Invalid pin %hhu\n", pin); return; } stm32_unconfiggpio(cfgset); }
static uint8_t stm32_gpio_get(void *driver_data, uint8_t pin) { uint32_t cfgset; int ret; lldbg("%s: pin=%hhu\n", __func__, pin); ret = map_pin_nr_to_cfgset(pin, &cfgset); if (ret) { lldbg("%s: Invalid pin %hhu\n", pin); return -EINVAL; } return stm32_gpioread(cfgset); }
static void stm32_gpio_set(void *driver_data, uint8_t pin, uint8_t val) { uint32_t cfgset; int ret; lldbg("%s: pin=%hhu, val=%d\n", __func__, pin, val); ret = map_pin_nr_to_cfgset(pin, &cfgset); if (ret) { lldbg("%s: Invalid pin %hhu\n", pin); return; } stm32_gpiowrite(cfgset, val); }
static int stm32_gpio_set_triggering(void *driver_data, uint8_t pin, int trigger) { uint32_t cfgset; int ret = 0; lldbg("%s: pin=%hhu, trigger=0x%x\n", __func__, pin, trigger); ret = map_pin_nr_to_cfgset(pin, &cfgset); if (ret) { lldbg("%s: Invalid pin %hhu\n", pin); return ret; } switch(trigger) { case IRQ_TYPE_NONE: stm32_gpio[pin].flags &= ~(STM32_GPIO_FLAG_RISING); stm32_gpio[pin].flags &= ~(STM32_GPIO_FLAG_FALLING); break; case IRQ_TYPE_EDGE_RISING: stm32_gpio[pin].flags |= STM32_GPIO_FLAG_RISING; stm32_gpio[pin].flags &= ~(STM32_GPIO_FLAG_FALLING); break; case IRQ_TYPE_EDGE_FALLING: stm32_gpio[pin].flags &= ~(STM32_GPIO_FLAG_RISING); stm32_gpio[pin].flags |= STM32_GPIO_FLAG_FALLING; break; case IRQ_TYPE_EDGE_BOTH: stm32_gpio[pin].flags |= STM32_GPIO_FLAG_RISING; stm32_gpio[pin].flags |= STM32_GPIO_FLAG_FALLING; break; /* Level IRQ: not supported by low level STM32 gpio support */ case IRQ_TYPE_LEVEL_HIGH: case IRQ_TYPE_LEVEL_LOW: default: return -EINVAL; } /* Install handler with edge triggering settings */ stm32_gpiosetevent_priv(cfgset, stm32_gpio[pin].flags & STM32_GPIO_FLAG_RISING, stm32_gpio[pin].flags & STM32_GPIO_FLAG_FALLING, true, (xcpt_priv_t) stm32_gpio[pin].isr, NULL); return ret; }
static void stm32_gpio_set_direction_in(void *driver_data, uint8_t pin) { uint32_t cfgset; int ret; lldbg("%s: pin=%hhu\n", __func__, pin); ret = map_pin_nr_to_cfgset(pin, &cfgset); if (ret) { lldbg("%s: Invalid pin %hhu\n", pin); return; } // Configure pin as input, floating cfgset |= GPIO_INPUT | GPIO_FLOAT; lldbg("cfgset=0x%x\n", cfgset); ret = stm32_configgpio(cfgset); if (ret) lldbg("%s: stm32_configgpio returns %d\n", ret); }
static int stm32_gpio_unmask_irq(void *driver_data, uint8_t pin) { uint32_t cfgset; int ret = 0; lldbg("%s: pin=%hhu\n", __func__, pin); ret = map_pin_nr_to_cfgset(pin, &cfgset); if (ret) { lldbg("%s: Invalid pin %hhu\n", pin); return ret; } /* Re-install handler */ stm32_gpiosetevent_priv(cfgset, stm32_gpio[pin].flags & STM32_GPIO_FLAG_RISING, stm32_gpio[pin].flags & STM32_GPIO_FLAG_FALLING, true, (xcpt_priv_t) stm32_gpio[pin].isr, NULL); return ret; }
static int stm32_gpio_mask_irq(void *driver_data, uint8_t pin) { uint32_t cfgset; int ret = 0; lldbg("%s: pin=%hhu\n", __func__, pin); ret = map_pin_nr_to_cfgset(pin, &cfgset); if (ret) { lldbg("%s: Invalid pin %hhu\n", pin); return ret; } /* Mask interrupt */ stm32_gpiosetevent_priv(cfgset, false, false, true, (xcpt_priv_t) stm32_gpio[pin].isr, NULL); return ret; }