static int mc34708_regulator_init(struct mc34708 *mc34708)
{
unsigned int value, register_mask;
pmic_read_reg(REG_MC34708_IDENTIFICATION, &value, 0xffffff);
pr_info("PMIC MC34708 ID:0x%x\n", value);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_MODE_0, &value, 0xffffff);
value &= ~(REG_MODE_0_ALL_MASK | USB_EN_MASK);
value |= REG_MODE_0_ALL_MASK;
pmic_write_reg(REG_MC34708_MODE_0, value, 0xffffff);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_SW_1_2_OP, &value, 0xffffff);
value &= ~REG_SW_1_2_MASK;
value |= REG_SW_1_2_VALUE;
pmic_write_reg(REG_MC34708_SW_1_2_OP, value, 0xffffff);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_SW_3_4_5_OP, &value, 0xffffff);
value &= ~REG_SW_3_4_5_MASK;
value |= REG_SW_3_4_5_VALUE;
pmic_write_reg(REG_MC34708_SW_3_4_5_OP, value, 0xffffff);
/* enable standby controll for mode0 regulators */
pmic_read_reg(REG_MC34708_SWBST, &value, 0xffffff);
value &= ~REG_SWBST_MODE_MASK;
value |= REG_SWBST_MODE_VALUE;
pmic_write_reg(REG_MC34708_SWBST, value, 0xffffff);
/* clear SWHOLD bit to enable USB MUX */
pmic_read_reg(REG_MC34708_USB_CONTROL, &value, 0xffffff);
value &= ~SWHOLD_MASK;
pmic_write_reg(REG_MC34708_USB_CONTROL, value, 0xffffff);
pr_info("Initializing mc34708 regulators for mx50 rdp.\n");
mc34708_register_regulator(mc34708, MC34708_SW1A, &sw1a_init);
mc34708_register_regulator(mc34708, MC34708_SW1B, &sw1b_init);
mc34708_register_regulator(mc34708, MC34708_SW2, &sw2_init);
mc34708_register_regulator(mc34708, MC34708_SW3, &sw3_init);
mc34708_register_regulator(mc34708, MC34708_SW4A, &sw4a_init);
mc34708_register_regulator(mc34708, MC34708_SW4B, &sw4b_init);
mc34708_register_regulator(mc34708, MC34708_SW5, &sw5_init);
mc34708_register_regulator(mc34708, MC34708_SWBST, &swbst_init);
mc34708_register_regulator(mc34708, MC34708_VPLL, &vpll_init);
mc34708_register_regulator(mc34708, MC34708_VREFDDR, &vrefddr_init);
mc34708_register_regulator(mc34708, MC34708_VDAC, &vdac_init);
mc34708_register_regulator(mc34708, MC34708_VUSB, &vusb_init);
mc34708_register_regulator(mc34708, MC34708_VUSB2, &vusb2_init);
mc34708_register_regulator(mc34708, MC34708_VGEN1, &vgen1_init);
mc34708_register_regulator(mc34708, MC34708_VGEN2, &vgen2_init);
regulator_has_full_constraints();
return 0;
}
static int mc34708_regulator_init(struct mc34708 *mc34708)
{
unsigned int value;
pmic_read_reg(REG_MC34708_IDENTIFICATION, &value, 0xffffff);
pr_info("PMIC MC34708 ID:0x%x\n", value);
/* setting switch operating mode for SW1/2 regulators */
pmic_read_reg(REG_MC34708_SW_1_2_OP, &value, 0xffffff);
value &= ~REG_SW_1_2_MASK;
value |= REG_SW_1_2_VALUE;
pmic_write_reg(REG_MC34708_SW_1_2_OP, value, 0xffffff);
/* setting switch operating mode for SW3/4/5 regulators */
pmic_read_reg(REG_MC34708_SW_3_4_5_OP, &value, 0xffffff);
value &= ~REG_SW_3_4_5_MASK;
value |= REG_SW_3_4_5_VALUE;
pmic_write_reg(REG_MC34708_SW_3_4_5_OP, value, 0xffffff);
/* setting switch operating mode for SWBST regulators */
pmic_read_reg(REG_MC34708_SWBST, &value, 0xffffff);
value &= ~REG_SWBST_MODE_MASK;
value |= REG_SWBST_MODE_VALUE;
pmic_write_reg(REG_MC34708_SWBST, value, 0xffffff);
/* clear SWHOLD bit to enable USB MUX */
pmic_read_reg(REG_MC34708_USB_CONTROL, &value, 0xffffff);
value &= ~SWHOLD_MASK;
pmic_write_reg(REG_MC34708_USB_CONTROL, value, 0xffffff);
/* enable WDI reset*/
pmic_read_reg(REG_MC34708_POWER_CTL2, &value, 0xffffff);
value |= 0x1000;
pmic_write_reg(REG_MC34708_POWER_CTL2, value, 0xffffff);
mc34708_register_regulator(mc34708, MC34708_SW1A, &sw1a_init);
mc34708_register_regulator(mc34708, MC34708_SW1B, &sw1b_init);
mc34708_register_regulator(mc34708, MC34708_SW2, &sw2_init);
mc34708_register_regulator(mc34708, MC34708_SW3, &sw3_init);
mc34708_register_regulator(mc34708, MC34708_SW4A, &sw4a_init);
mc34708_register_regulator(mc34708, MC34708_SW4B, &sw4b_init);
mc34708_register_regulator(mc34708, MC34708_SW5, &sw5_init);
mc34708_register_regulator(mc34708, MC34708_SWBST, &swbst_init);
mc34708_register_regulator(mc34708, MC34708_VPLL, &vpll_init);
mc34708_register_regulator(mc34708, MC34708_VREFDDR, &vrefddr_init);
mc34708_register_regulator(mc34708, MC34708_VDAC, &vdac_init);
mc34708_register_regulator(mc34708, MC34708_VUSB, &vusb_init);
mc34708_register_regulator(mc34708, MC34708_VUSB2, &vusb2_init);
mc34708_register_regulator(mc34708, MC34708_VGEN1, &vgen1_init);
mc34708_register_regulator(mc34708, MC34708_VGEN2, &vgen2_init);
regulator_has_full_constraints();
return 0;
}
