/* AMD Family10 machine check */ enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c) { enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(c); if (amd_k8_mcheck_init(c) == mcheck_none) return mcheck_none; if (quirkflag == MCEQUIRK_F10_GART) mcequirk_amd_apply(quirkflag); x86_mce_callback_register(amd_f10_handler); mce_recoverable_register(mc_amd_recoverable_scan); mce_register_addrcheck(mc_amd_addrcheck); return mcheck_amd_famXX; }
enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *ci) { uint32_t i; enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(ci); /* Assume that machine check support is available. * The minimum provided support is at least the K8. */ mce_handler_init(); x86_mce_vector_register(mcheck_cmn_handler); mce_need_clearbank_register(amd_need_clearbank_scan); for ( i = 0; i < nr_mce_banks; i++ ) { if ( quirkflag == MCEQUIRK_K8_GART && i == 4 ) mcequirk_amd_apply(quirkflag); else { /* Enable error reporting of all errors */ wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL); wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL); } } if ( ci->x86 == 0xf ) return mcheck_amd_k8; if ( quirkflag == MCEQUIRK_F10_GART ) mcequirk_amd_apply(quirkflag); x86_mce_callback_register(amd_f10_handler); mce_recoverable_register(mc_amd_recoverable_scan); mce_register_addrcheck(mc_amd_addrcheck); return mcheck_amd_famXX; }