/*
* Routines to support the NETtel software reset button.
*/
void reset_button(int irq, void *dev_id, struct pt_regs *regs)
{
static int inbutton = 0;
/*
* IRQ7 is not maskable by the CPU core. It is possible
* that switch bounce may get us back here before we have
* really serviced the interrupt.
*/
if (inbutton)
return;
inbutton = 1;
/* Disable interrupt at SIM - best we can do... */
mcf_setimr(mcf_getimr() | MCFSIM_IMR_EINT7);
#ifdef CONFIG_LEDMAN
ledman_signalreset();
#endif
/* Don't leave here 'till button is no longer pushed! */
for (;;) {
if ((mcf_getipr() & MCFSIM_IMR_EINT7) == 0)
break;
}
#ifndef CONFIG_LEDMAN
HARD_RESET_NOW();
/* Should never get here... */
#endif
inbutton = 0;
/* Interrupt service done, enable it again */
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT7);
}
static void __init m5407_uart_init_line(int line, int irq)
{
if (line == 0) {
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
} else if (line == 1) {
writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
}
}
static int __init watchdog_init(void)
{
printk("WATCHDOG: initializing at vector=%d\n", IRQ_WATCHDOG);
request_irq(IRQ_WATCHDOG, watchdog_timeout, SA_INTERRUPT,
"Watchdog Timer", NULL);
watchdog_timerlist.expires = jiffies + TIMEPOLL;
add_timer(&watchdog_timerlist);
#ifdef CONFIG_M5272
{
volatile unsigned long *icrp;
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR4);
*icrp = (*icrp & 0x77707777) | 0x000E0000;
}
#else
{
volatile unsigned char *mbar;
mbar = (volatile unsigned char *) MCF_MBAR;
*(mbar + MCFSIM_SWDICR) = MCFSIM_ICR_LEVEL1 | MCFSIM_ICR_PRI3;
*(mbar + MCFSIM_SWIVR) = IRQ_WATCHDOG;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_SWD);
}
#endif
watchdog_enable();
return(0);
}
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
/* Set up TIMER 1 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER1ICR);
#ifdef CONFIG_NETtel
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3;
request_irq(30, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
reset_setupbutton();
#else
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI3;
request_irq(29, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#endif
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER1);
}
void coldfire_timer_init(void (*handler)(int, void *, struct pt_regs *))
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
/* Set up TIMER 1 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE1);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_BUSCLK / 16) / HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER1ICR);
#if defined(CONFIG_FLASH_SNAPGEAR) || defined(CONFIG_CLEOPATRA)
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3;
request_irq(30, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#else
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI3;
request_irq(29, handler, SA_INTERRUPT, "ColdFire Timer", NULL);
#endif
#ifdef CONFIG_RESETSWITCH
/* This is not really the right place to do this... */
reset_setupbutton();
#endif
#ifdef CONFIG_HIGHPROFILE
coldfire_profile_init();
#endif
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER1);
}
void watchdog_disable(void)
{
#ifdef CONFIG_M5272
*(volatile unsigned short *)(MCF_MBAR + MCFSIM_WRRR) = 0xFFFE;
*(volatile unsigned short *)(MCF_MBAR + MCFSIM_WIRR) = 0x0000;
*(volatile unsigned short *)(MCF_MBAR + MCFSIM_WCR) = 0x0000;
#else
volatile unsigned char *mbar = (volatile unsigned char *) MCF_MBAR;
/*
If watchdog is set to 'reset', this function is useless...
If timer is disabled, this reset will occour at once.
*/
*(mbar + MCFSIM_SWSR) = 0x55;
*(mbar + MCFSIM_SWSR) = 0xaa;
#if 0
/*
SYPCR Can only be written once after system reset!
This will probably be ignored according to MCF5206E User Manual
*/
*(mbar + MCFSIM_SYPCR) = 0x00 /*0x3e*/;
#endif
mcf_setimr(mcf_getimr() | MCFSIM_IMR_SWD);
#endif
del_timer(&watchdog_timerlist);
}
void coldfire_fast_init(void)
{
volatile unsigned short *timerp;
#ifdef CONFIG_M5272
volatile unsigned long *icrp;
#else
volatile unsigned char *icrp;
#endif
printk("FASTCLK: lodging timer2=%d as profile timer\n", FAST_HZ);
/* Set up TIMER 2 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_CLK / 16) / FAST_HZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
#ifdef CONFIG_M5272
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
*icrp = 0x00000e00; /* TMR2 with priority 7 */
request_irq(70, coldfire_fast_tick, (SA_INTERRUPT | IRQ_FLG_FAST),
"Fast Timer", NULL);
#else
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER2ICR);
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3;
request_irq(31, coldfire_fast_tick, (SA_INTERRUPT | IRQ_FLG_FAST),
"Fast Timer", NULL);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER2);
#endif
}
void reset_setupbutton(void)
{
volatile unsigned char *mbar;
mbar = (volatile unsigned char *) MCF_MBAR;
*(mbar + MCFSIM_AVR) |= MCFSIM_IMR_EINT7;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT7);
request_irq(31, reset_button, (SA_INTERRUPT | IRQ_FLG_FAST),
"Reset Button", NULL);
}
void mcf_autovector(unsigned int vec)
{
volatile unsigned char *mbar;
if ((vec >= 25) && (vec <= 31)) {
mbar = (volatile unsigned char *) MCF_MBAR;
vec = 0x1 << (vec - 24);
*(mbar + MCFSIM_AVR) |= vec;
mcf_setimr(mcf_getimr() & ~vec);
}
}
void dac0800_init(void)
{
volatile unsigned char *mbarp, *dmap;
unsigned long imr;
unsigned int icr;
int result;
/* Register dac0800 as character device */
result = register_chrdev(DAC0800_MAJOR, "dac0800", &dac0800_fops);
if (result < 0) {
printk(KERN_WARNING "DAC0800: can't get major %d\n",
DAC0800_MAJOR);
return;
}
printk ("DAC0800: Copyright (C) 1999, Greg Ungerer "
"([email protected])\n");
/* Install ISR (interrupt service routine) */
result = request_irq(DAC0800_VEC, dac0800_isr, SA_INTERRUPT,
"DAC0800", NULL);
if (result) {
printk ("DAC0800: IRQ %d already in use\n", DAC0800_VEC);
return;
}
/* Set interrupt vector location */
dmap = (volatile unsigned char *) dma_base_addr[DAC0800_DMA_CHAN];
dmap[MCFDMA_DIVR] = DAC0800_VEC;
/* Set interrupt level and priority */
switch (DAC0800_DMA_CHAN) {
case 1: icr = MCFSIM_DMA1ICR ; imr = MCFSIM_IMR_DMA1; break;
case 2: icr = MCFSIM_DMA2ICR ; imr = MCFSIM_IMR_DMA2; break;
case 3: icr = MCFSIM_DMA3ICR ; imr = MCFSIM_IMR_DMA3; break;
default: icr = MCFSIM_DMA0ICR ; imr = MCFSIM_IMR_DMA0; break;
}
mbarp = (volatile unsigned char *) MCF_MBAR;
mbarp[icr] = MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1;
mcf_setimr(mcf_getimr() & ~imr);
/* Request DMA channel */
printk ("DAC0800: requesting DMA channel %d\n", DAC0800_DMA_CHAN);
result = request_dma(DAC0800_DMA_CHAN, "dac0800");
if (result) {
printk ("DAC0800: dma channel %d already in use\n",
DAC0800_DMA_CHAN);
return;
}
/* Program default timer rate */
dac0800_setclk(8000);
}
void mcf_autovector(unsigned int vec)
{
volatile unsigned char *mbar;
unsigned char icr;
if ((vec >= 25) && (vec <= 31)) {
vec -= 25;
mbar = (volatile unsigned char *) MCF_MBAR;
icr = MCFSIM_ICR_AUTOVEC | (vec << 3);
*(mbar + MCFSIM_ICR1 + vec) = icr;
vec = 0x1 << (vec + 1);
mcf_setimr(mcf_getimr() & ~vec);
}
}
void mcf_settimericr(unsigned int timer, unsigned int level)
{
volatile unsigned char *icrp;
unsigned int icr, imr;
if (timer <= 2) {
switch (timer) {
case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
}
icrp = (volatile unsigned char *) (MCF_MBAR + icr);
*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
mcf_setimr(mcf_getimr() & ~imr);
}
}
void coldfire_profile_init(void)
{
volatile unsigned short *timerp;
volatile unsigned char *icrp;
printk("PROFILE: lodging timer2=%d as profile timer\n", PROFILEHZ);
/* Set up TIMER 2 as poll clock */
timerp = (volatile unsigned short *) (MCF_MBAR + MCFTIMER_BASE2);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_DISABLE;
timerp[MCFTIMER_TRR] = (unsigned short) ((MCF_BUSCLK / 16) / PROFILEHZ);
timerp[MCFTIMER_TMR] = MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_TIMER2ICR);
*icrp = MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3;
request_irq(31, coldfire_profile_tick, (SA_INTERRUPT | IRQ_FLG_FAST),
"Profile Timer", NULL);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_TIMER2);
}
/*
* Process a watchdog timeout interrupt. For a normal clean watchdog
* we just do a process dump. For old broken 5307 we need to verify
* if this was a real watchdog event or not...
*/
void watchdog_timeout(int irq, void *dummy, struct pt_regs *fp)
{
#ifdef CONFIG_OLDMASK
/*
* Debuging code for software watchdog. If we get in here
* and timer interrupt counts don't match we know that a
* bad external bus cycle must have locked the CPU.
*/
if ((swt_doit++ > TIMEDELAY) &&
((swt_lastjiffies + swt_reference) > jiffies)) {
if (swt_inwatchdog) {
cli();
watchdog_disable();
mcf_setimr(mcf_getimr() | MCFSIM_IMR_SWD);
printk("%s(%d): Double WATCHDOG PANIC!!\n",
__FILE__, __LINE__);
for (;;)
;
}
swt_inwatchdog++;
swt_doit = TIMEDELAY - 8; /* 8 seconds grace */
printk("WATCHDOG: expired last=%d(%d) jiffies=%d!\n",
swt_lastjiffies, swt_reference, jiffies);
dump(fp);
force_sig(SIGSEGV, current);
swt_inwatchdog = 0;
}
swt_lastjiffies = jiffies;
#else
printk("WATCHDOG: expired!\n");
dump(fp);
#endif /* CONFIG_OLDMASK */
}
static void __inline__ mcf_disablevec(void)
{
mcf_setimr(mcf_getimr() | MCFSIM_IMR_EINT7);
}
static int init_port(void)
{
unsigned long flags;
/* Check io region*/
#ifdef LIRC_PORT
if((check_region(port,8))==-EBUSY)
{
#if 0
/* this is the correct behaviour but many people have
the serial driver compiled into the kernel... */
printk(KERN_ERR LIRC_DRIVER_NAME
": port %04x already in use\n", port);
return(-EBUSY);
#else
printk(KERN_ERR LIRC_DRIVER_NAME
": port %04x already in use, proceding anyway\n", port);
printk(KERN_WARNING LIRC_DRIVER_NAME
": compile the serial port driver as module and\n");
printk(KERN_WARNING LIRC_DRIVER_NAME
": make sure this module is loaded first\n");
release_region(port,8);
#endif
}
/* Reserve io region. */
request_region(port, 8, LIRC_DRIVER_NAME);
#endif
save_flags(flags);cli();
#ifndef CONFIG_COLDFIRE
/* Set DLAB 0. */
soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB));
/* First of all, disable all interrupts */
soutp(UART_IER, sinp(UART_IER)&
(~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI)));
/* Clear registers. */
sinp(UART_LSR);
sinp(UART_RX);
sinp(UART_IIR);
sinp(UART_MSR);
/* Set line for power source */
soutp(UART_MCR, LIRC_OFF);
/* Clear registers again to be sure. */
sinp(UART_LSR);
sinp(UART_RX);
sinp(UART_IIR);
sinp(UART_MSR);
#ifdef LIRC_SERIAL_IRDEO
/* setup port to 7N1 @ 115200 Baud */
/* 7N1+start = 9 bits at 115200 ~ 3 bits at 38kHz */
/* Set DLAB 1. */
soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB);
/* Set divisor to 1 => 115200 Baud */
soutp(UART_DLM,0);
soutp(UART_DLL,1);
/* Set DLAB 0 + 7N1 */
soutp(UART_LCR,UART_LCR_WLEN7);
/* THR interrupt already disabled at this point */
#endif
#else /* CONFIG_COLDFIRE */
{
volatile unsigned char *uartp;
#ifdef CONFIG_M5272
volatile unsigned long *icrp;
#else
volatile unsigned char *icrp;
#endif
/*
* we need a fast timer
*/
coldfire_fast_init();
/*
* Setup the interrupts
*/
#ifdef CONFIG_M5272
#ifndef LIRC_PORT
/* nothing to do */
#else
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR2);
switch (LIRC_PORT) {
case MCFUART_BASE1:
*icrp = 0xe0000000;
break;
case MCFUART_BASE2:
*icrp = 0x0e000000;
break;
default:
printk("SERIAL: don't know how to handle UART %d interrupt?\n",
LIRC_PORT;
return;
}
#endif
#else
switch (LIRC_PORT) {
case MCFUART_BASE1:
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_UART1ICR);
*icrp = /*MCFSIM_ICR_AUTOVEC |*/ MCFSIM_ICR_LEVEL6 |
MCFSIM_ICR_PRI1;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
break;
case MCFUART_BASE2:
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_UART2ICR);
*icrp = /*MCFSIM_ICR_AUTOVEC |*/ MCFSIM_ICR_LEVEL6 |
MCFSIM_ICR_PRI2;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
break;
default:
printk("SERIAL: don't know how to handle UART %d interrupt?\n",
LIRC_PORT);
return(-EIO);
}
soutp(MCFUART_UIVR, LIRC_IRQ);
#endif
#ifdef LIRC_PORT
/*
* disable all interrupts
*/
soutp(MCFUART_UIMR, 0);
soutp(MCFUART_UCR, MCFUART_UCR_CMDRESETRX); /* reset RX */
soutp(MCFUART_UCR, MCFUART_UCR_CMDRESETTX); /* reset TX */
soutp(MCFUART_UCR, MCFUART_UCR_CMDRESETMRPTR); /* reset MR pointer */
/*
* Set port for defined baud , 8 data bits, 1 stop bit, no parity.
*/
soutp(MCFUART_UMR, MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8);
soutp(MCFUART_UMR, MCFUART_MR2_STOP1);
#define clk ((MCF_CLK / 32) / 115200)
soutp(MCFUART_UBG1, (clk & 0xff00) >> 8); /* set msb baud */
soutp(MCFUART_UBG2, (clk & 0xff)); /* set lsb baud */
#undef clk
soutp(MCFUART_UCSR, MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER);
soutp(MCFUART_UCR, 0 /* MCFUART_UCR_RXENABLE */);
/*
* Allow COS interrupts
*/
soutp(MCFUART_UACR, MCFUART_UACR_IEC);
/*
* turn on RTS for power
*/
soutp(MCFUART_UOP1, MCFUART_UOP_RTS);
#endif /* LIRC_PORT */
}
#endif /* CONFIG_COLDFIRE */
restore_flags(flags);
/* If pin is high, then this must be an active low receiver. */
if(sense==-1)
{
#if DAVIDM
/* wait 1 sec for the power supply */
# ifdef KERNEL_2_1
sleep_on_timeout(&power_supply_queue,HZ);
# else
init_timer(&power_supply_timer);
power_supply_timer.expires=jiffies+HZ;
power_supply_timer.data=(unsigned long) current;
power_supply_timer.function=power_supply_up;
add_timer(&power_supply_timer);
sleep_on(&power_supply_queue);
del_timer(&power_supply_timer);
# endif
#ifndef LIRC_PORT
sense=(pin_status & LIRC_SIGNAL_PIN) ? 1:0;
#else
sense=(sinp(UART_MSR) & LIRC_SIGNAL_PIN) ? 1:0;
#endif
#else
sense = 0;
#endif /* DAVIDM */
printk(KERN_INFO LIRC_DRIVER_NAME ": auto-detected active "
"%s receiver\n",sense ? "low":"high");
}
else
{
printk(KERN_INFO LIRC_DRIVER_NAME ": Manually using active "
"%s receiver\n",sense ? "low":"high");
};
return 0;
}
/*
* Based on the line number set up the internal interrupt stuff.
*/
static void mcfrs_irqinit(struct mcf_serial *info)
{
#if defined(CONFIG_M5272)
volatile unsigned long *icrp;
volatile unsigned long *portp;
volatile unsigned char *uartp;
uartp = info->addr;
icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR2);
switch (info->line) {
case 0:
*icrp = 0xe0000000;
break;
case 1:
*icrp = 0x0e000000;
break;
default:
printk("MCFRS: don't know how to handle UART %d interrupt?\n",
info->line);
return;
}
/* Enable the output lines for the serial ports */
portp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PBCNT);
*portp = (*portp & ~0x000000ff) | 0x00000055;
portp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PDCNT);
*portp = (*portp & ~0x000003fc) | 0x000002a8;
#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
volatile unsigned char *icrp, *uartp;
volatile unsigned long *imrp;
uartp = info->addr;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFICM_INTC0 +
MCFINTC_ICR0 + MCFINT_UART0 + info->line);
*icrp = 0x30 + info->line; /* level 6, line based priority */
imrp = (volatile unsigned long *) (MCF_MBAR + MCFICM_INTC0 +
MCFINTC_IMRL);
*imrp &= ~((1 << (info->irq - MCFINT_VECBASE)) | 1);
#if defined(CONFIG_M527x)
{
/*
* External Pin Mask Setting & Enable External Pin for Interface
* [email protected]
*/
u16 *serpin_enable_mask;
serpin_enable_mask = (u16 *) (MCF_IPSBAR + MCF_GPIO_PAR_UART);
if (info->line == 0)
*serpin_enable_mask |= UART0_ENABLE_MASK;
else if (info->line == 1)
*serpin_enable_mask |= UART1_ENABLE_MASK;
else if (info->line == 2)
*serpin_enable_mask |= UART2_ENABLE_MASK;
}
#endif
#if defined(CONFIG_M528x)
/* make sure PUAPAR is set for UART0 and UART1 */
if (info->line < 2) {
volatile unsigned char *portp = (volatile unsigned char *) (MCF_MBAR + MCF5282_GPIO_PUAPAR);
*portp |= (0x03 << (info->line * 2));
}
#endif
#elif defined(CONFIG_M520x)
volatile unsigned char *icrp, *uartp;
volatile unsigned long *imrp;
uartp = info->addr;
icrp = (volatile unsigned char *) (MCF_MBAR + MCFICM_INTC0 +
MCFINTC_ICR0 + MCFINT_UART0 + info->line);
*icrp = 0x03;
imrp = (volatile unsigned long *) (MCF_MBAR + MCFICM_INTC0 +
MCFINTC_IMRL);
*imrp &= ~((1 << (info->irq - MCFINT_VECBASE)) | 1);
if (info->line < 2) {
unsigned short *uart_par;
uart_par = (unsigned short *)(MCF_IPSBAR + MCF_GPIO_PAR_UART);
if (info->line == 0)
*uart_par |= MCF_GPIO_PAR_UART_PAR_UTXD0
| MCF_GPIO_PAR_UART_PAR_URXD0;
else if (info->line == 1)
*uart_par |= MCF_GPIO_PAR_UART_PAR_UTXD1
| MCF_GPIO_PAR_UART_PAR_URXD1;
} else if (info->line == 2) {
unsigned char *feci2c_par;
feci2c_par = (unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C);
*feci2c_par &= ~0x0F;
*feci2c_par |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2
| MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
}
#elif defined(CONFIG_M532x)
volatile unsigned char *uartp;
uartp = info->addr;
switch (info->line) {
case 0:
MCF_INTC0_ICR26 = 0x3;
MCF_INTC0_CIMR = 26;
/* GPIO initialization */
MCF_GPIO_PAR_UART |= 0x000F;
break;
case 1:
MCF_INTC0_ICR27 = 0x3;
MCF_INTC0_CIMR = 27;
/* GPIO initialization */
MCF_GPIO_PAR_UART |= 0x0FF0;
break;
case 2:
MCF_INTC0_ICR28 = 0x3;
MCF_INTC0_CIMR = 28;
/* GPIOs also must be initalized, depends on board */
break;
}
#else
volatile unsigned char *icrp, *uartp;
switch (info->line) {
case 0:
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_UART1ICR);
*icrp = /*MCFSIM_ICR_AUTOVEC |*/ MCFSIM_ICR_LEVEL6 |
MCFSIM_ICR_PRI1;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
break;
case 1:
icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_UART2ICR);
*icrp = /*MCFSIM_ICR_AUTOVEC |*/ MCFSIM_ICR_LEVEL6 |
MCFSIM_ICR_PRI2;
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
break;
default:
printk("MCFRS: don't know how to handle UART %d interrupt?\n",
info->line);
return;
}
uartp = info->addr;
uartp[MCFUART_UIVR] = info->irq;
#endif
/* Clear mask, so no surprise interrupts. */
uartp[MCFUART_UIMR] = 0;
if (request_irq(info->irq, mcfrs_interrupt, IRQF_DISABLED,
"ColdFire UART", NULL)) {
printk("MCFRS: Unable to attach ColdFire UART %d interrupt "
"vector=%d\n", info->line, info->irq);
}
return;
}
void m5249audio_init(void)
{
printk("M5249AUDIO: (C) Copyright 2002, "
"Greg Ungerer ([email protected])\n");
if (register_chrdev(SOUND_MAJOR, "sound", &m5249audio_fops) < 0) {
printk(KERN_WARNING "SOUND: failed to register major %d\n",
SOUND_MAJOR);
return;
}
m5249audio_buf = kmalloc(BUFSIZE, GFP_KERNEL);
if (m5249audio_buf == NULL) {
printk("M5249AUDIO: failed to allocate DMA[%d] buffer\n",
BUFSIZE);
}
#ifdef CONFIG_AUDIOIRQ
#ifdef CONFIG_AUDIOIRQASM
/* Install fast interrupt handler */
printk("M5249AUDIO: fast interrupt handler irq=%d\n",
M5249AUDIO_TXIRQ);
*((unsigned long *) (M5249AUDIO_TXIRQ * 4)) =
(unsigned long) m5249audio_isr;
#else
/* Re-direct TX empty FIFO audio interrupt. */
printk("M5249AUDIO: standard interrupt handler, irq=%d\n",
M5249AUDIO_TXIRQ);
if (request_irq(M5249AUDIO_TXIRQ, m5249audio_isr,
(SA_INTERRUPT | IRQ_FLG_FAST), "audio", NULL)) {
printk("M5249AUDIO: IRQ %d already in use?\n",
M5249AUDIO_TXIRQ);
}
#endif
*reg32p(0x140) = 0x00007000;
#endif
#ifdef CONFIG_AUDIODMA
{
volatile unsigned char *dmap;
unsigned int icr;
printk("M5249AUDIO: DMA channel=%d, irq=%d\n",
M5249AUDIO_DMA, M5249AUDIO_DMAIRQ);
if (request_irq(M5249AUDIO_DMAIRQ, m5249audio_dmaisr,
(SA_INTERRUPT | IRQ_FLG_FAST), "audio(DMA)", NULL)) {
printk("M5249AUDIO: DMA IRQ %d already in use?\n",
M5249AUDIO_DMAIRQ);
}
dmap = (volatile unsigned char *) dma_base_addr[M5249AUDIO_DMA];
dmap[MCFDMA_DIVR] = M5249AUDIO_DMAIRQ;
/* Set interrupt level and priority */
switch (M5249AUDIO_DMA) {
case 1: icr=MCFSIM_DMA1ICR; m5249audio_imrbit=MCFSIM_IMR_DMA1; break;
case 2: icr=MCFSIM_DMA2ICR; m5249audio_imrbit=MCFSIM_IMR_DMA2; break;
case 3: icr=MCFSIM_DMA3ICR; m5249audio_imrbit=MCFSIM_IMR_DMA3; break;
default: icr=MCFSIM_DMA0ICR; m5249audio_imrbit=MCFSIM_IMR_DMA0; break;
}
*simp(icr) = MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3;
mcf_setimr(mcf_getimr() & ~m5249audio_imrbit);
/* Set DMA to use channel 0 for audio */
*reg8p(MCFA_DMACONF) = MCFA_DMA_0REQ;
*reg32p(MCFSIM2_DMAROUTE) = 0x00000080;
if (request_dma(M5249AUDIO_DMA, "audio")) {
printk("M5249AUDIO: DMA channel %d already in use?\n",
M5249AUDIO_DMA);
}
}
#endif
/* Unmute the DAC, set GPIO49 */
*reg32p(MCFSIM2_GPIO1FUNC) |= 0x00020000;
*reg32p(MCFSIM2_GPIO1ENABLE) |= 0x00020000;
m5249audio_unmute();
/* Power up the DAC, set GPIO39 */
*reg32p(MCFSIM2_GPIO1FUNC) |= 0x00000080;
*reg32p(MCFSIM2_GPIO1ENABLE) |= 0x00000080;
*reg32p(MCFSIM2_GPIO1WRITE) |= 0x00000080;
m5249audio_chipinit();
/* Dummy write to start outputing */
*reg32p(MCFA_PDOR3) = 0;
}
static void __inline__ mcf_ackvector(void)
{
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT7);
}
