static void __write_cpuxgpt(unsigned int reg_index, unsigned int value)
{
#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
/* DRV_WriteReg32(INDEX_BASE,reg_index); */
/* DRV_WriteReg32(CTL_BASE,value); */
mcusys_smc_write_phy(INDEX_BASE_PHY, reg_index);
mcusys_smc_write_phy(CTL_BASE_PHY, value);
#else
mcusys_smc_write(INDEX_BASE, reg_index);
mcusys_smc_write(CTL_BASE, value);
#endif
}
static inline void cpu_leave_lowpower(unsigned int cpu)
{
//HOTPLUG_INFO("cpu_leave_lowpower\n");
if (((cpu == 4) && (cpu_online(5) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 5) && (cpu_online(4) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 6) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(7) == 0)) ||
((cpu == 7) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(6) == 0)))
{
/* Enable CA15L snoop function */
#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write_phy(virt_to_phys(MP1_AXI_CONFIG), REG_READ(MP1_AXI_CONFIG) & ~ACINACTM);
#else //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write(MP1_AXI_CONFIG, REG_READ(MP1_AXI_CONFIG) & ~ACINACTM);
#endif //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
/* Enable snoop requests and DVM message requests */
REG_WRITE(CCI400_SI3_SNOOP_CONTROL, REG_READ(CCI400_SI3_SNOOP_CONTROL) | (SNOOP_REQ | DVM_MSG_REQ));
while (REG_READ(CCI400_STATUS) & CHANGE_PENDING);
}
/* Set the ACTLR.SMP bit to 1 for SMP mode */
__switch_to_smp();
/* Enable dcache */
__enable_dcache();
}
static unsigned int __read_cpuxgpt(unsigned int reg_index)
{
unsigned int value = 0;
#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
/* DRV_WriteReg32(INDEX_BASE,reg_index); */
mcusys_smc_write_phy(INDEX_BASE_PHY, reg_index);
#else
mcusys_smc_write(INDEX_BASE, reg_index);
#endif
value = __raw_readl(CTL_BASE);
return value;
}
/*
* static function
*/
static inline void cpu_enter_lowpower(unsigned int cpu)
{
//HOTPLUG_INFO("cpu_enter_lowpower\n");
if (((cpu == 4) && (cpu_online(5) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 5) && (cpu_online(4) == 0) && (cpu_online(6) == 0) && (cpu_online(7) == 0)) ||
((cpu == 6) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(7) == 0)) ||
((cpu == 7) && (cpu_online(4) == 0) && (cpu_online(5) == 0) && (cpu_online(6) == 0)))
{
#if 0
/* Clear the SCTLR C bit to prevent further data cache allocation */
__disable_dcache();
/* Clean and invalidate all data from the L1/L2 data cache */
inner_dcache_flush_L1();
//flush_cache_all();
/* Execute a CLREX instruction */
__asm__ __volatile__("clrex");
/* Clean all data from the L2 data cache */
inner_dcache_flush_L2();
#else
__disable_dcache__inner_flush_dcache_L1__inner_flush_dcache_L2();
#endif
/* Switch the processor from SMP mode to AMP mode by clearing the ACTLR SMP bit */
__switch_to_amp();
/* Execute an ISB instruction to ensure that all of the CP15 register changes from the previous steps have been committed */
isb();
/* Execute a DSB instruction to ensure that all cache, TLB and branch predictor maintenance operations issued by any processor in the multiprocessor device before the SMP bit was cleared have completed */
dsb();
/* Disable snoop requests and DVM message requests */
REG_WRITE(CCI400_SI3_SNOOP_CONTROL, REG_READ(CCI400_SI3_SNOOP_CONTROL) & ~(SNOOP_REQ | DVM_MSG_REQ));
while (REG_READ(CCI400_STATUS) & CHANGE_PENDING);
/* Disable CA15L snoop function */
#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write_phy(virt_to_phys(MP1_AXI_CONFIG), REG_READ(MP1_AXI_CONFIG) | ACINACTM);
#else //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
mcusys_smc_write(MP1_AXI_CONFIG, REG_READ(MP1_AXI_CONFIG) | ACINACTM);
#endif //#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
}
else
{
#if 0
/* Clear the SCTLR C bit to prevent further data cache allocation */
__disable_dcache();
/* Clean and invalidate all data from the L1 data cache */
inner_dcache_flush_L1();
//Just flush the cache.
//flush_cache_all();
/* Clean all data from the L2 data cache */
//__inner_clean_dcache_L2();
#else
//FIXME: why __disable_dcache__inner_flush_dcache_L1 fail but 2 steps ok?
//__disable_dcache__inner_flush_dcache_L1();
__disable_dcache__inner_flush_dcache_L1__inner_clean_dcache_L2();
#endif
/* Execute a CLREX instruction */
__asm__ __volatile__("clrex");
/* Switch the processor from SMP mode to AMP mode by clearing the ACTLR SMP bit */
__switch_to_amp();
}
}
