static void pyr_dsi_dbi_mode_set(struct drm_encoder * encoder, struct drm_display_mode * mode, struct drm_display_mode * adjusted_mode) { int ret = 0; struct drm_device * dev = encoder->dev; struct drm_psb_private * dev_priv = (struct drm_psb_private*)dev->dev_private; struct mdfld_dsi_encoder * dsi_encoder = MDFLD_DSI_ENCODER(encoder); struct mdfld_dsi_dbi_output * dsi_output = MDFLD_DSI_DBI_OUTPUT(dsi_encoder); struct mdfld_dsi_config * dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder); struct mdfld_dsi_connector * dsi_connector = dsi_config->connector; int pipe = dsi_connector->pipe; u8 param = 0; /*regs*/ u32 mipi_reg = MIPI; u32 dspcntr_reg = DSPACNTR; u32 pipeconf_reg = PIPEACONF; u32 reg_offset = 0; /*values*/ u32 dspcntr_val = dev_priv->dspcntr; u32 pipeconf_val = dev_priv->pipeconf; u32 h_active_area = mode->hdisplay; u32 v_active_area = mode->vdisplay; u32 mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX); if (dev_priv->platform_rev_id != MDFLD_PNW_A0) mipi_val = (PASS_FROM_SPHY_TO_AFE | TE_TRIGGER_GPIO_PIN); PSB_DEBUG_ENTRY("mipi_val =0x%x\n", mipi_val); PSB_DEBUG_ENTRY("type %s\n", (pipe == 2) ? "MIPI2" : "MIPI"); PSB_DEBUG_ENTRY("h %d v %d\n", mode->hdisplay, mode->vdisplay); if(pipe == 2) { mipi_reg = MIPI_C; dspcntr_reg = DSPCCNTR; pipeconf_reg = PIPECCONF; reg_offset = MIPIC_REG_OFFSET; dspcntr_val = dev_priv->dspcntr2; pipeconf_val = dev_priv->pipeconf2; } else { mipi_val |= 0x2; /*two lanes for port A and C respectively*/ } if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) { DRM_ERROR("hw begin failed\n"); return; } /*set up pipe related registers*/ REG_WRITE(mipi_reg, mipi_val); REG_READ(mipi_reg); pyr_dsi_controller_dbi_init(dsi_config, pipe); msleep(20); REG_WRITE(dspcntr_reg, dspcntr_val); REG_READ(dspcntr_reg); /*20ms delay before sending exit_sleep_mode*/ msleep(20); /*send exit_sleep_mode DCS*/ ret = mdfld_dsi_dbi_send_dcs(dsi_output, exit_sleep_mode, NULL, 0, CMD_DATA_SRC_SYSTEM_MEM); if(ret) { DRM_ERROR("sent exit_sleep_mode faild\n"); goto out_err; } if (dev_priv->platform_rev_id != MDFLD_PNW_A0) { /*send set_tear_on DCS*/ ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on, ¶m, 1, CMD_DATA_SRC_SYSTEM_MEM); if(ret) { DRM_ERROR("%s - sent set_tear_on faild\n", __func__); goto out_err; } } /*do some init stuff*/ mdfld_dsi_brightness_init(dsi_config, pipe); mdfld_dsi_gen_fifo_ready (dev, (MIPIA_GEN_FIFO_STAT_REG + reg_offset), HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY); REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR); REG_READ(pipeconf_reg); /*TODO: this looks ugly, try to move it to CRTC mode setting*/ if(pipe == 2) { dev_priv->pipeconf2 |= PIPEACONF_DSR; } else { dev_priv->pipeconf |= PIPEACONF_DSR; } PSB_DEBUG_ENTRY("pipeconf %x\n", REG_READ(pipeconf_reg)); ret = mdfld_dsi_dbi_update_area(dsi_output, 0, 0, h_active_area - 1, v_active_area - 1); if(ret) { DRM_ERROR("update area failed\n"); goto out_err; } out_err: ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); if(ret) { DRM_ERROR("mode set failed\n"); } else { PSB_DEBUG_ENTRY("mode set done successfully\n"); } }
static void mdfld_dsi_dbi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { int ret = 0; struct drm_device *dev = encoder->dev; struct drm_psb_private *dev_priv = dev->dev_private; struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder); struct mdfld_dsi_dbi_output *dsi_output = MDFLD_DSI_DBI_OUTPUT(dsi_encoder); struct mdfld_dsi_config *dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder); struct mdfld_dsi_connector *dsi_connector = dsi_config->connector; int pipe = dsi_connector->pipe; u8 param = 0; /* Regs */ u32 mipi_reg = MIPI; u32 dspcntr_reg = DSPACNTR; u32 pipeconf_reg = PIPEACONF; u32 reg_offset = 0; /* Values */ u32 dspcntr_val = dev_priv->dspcntr; u32 pipeconf_val = dev_priv->pipeconf; u32 h_active_area = mode->hdisplay; u32 v_active_area = mode->vdisplay; u32 mipi_val; mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX | TE_TRIGGER_GPIO_PIN); dev_dbg(dev->dev, "mipi_val =0x%x\n", mipi_val); dev_dbg(dev->dev, "type %s\n", (pipe == 2) ? "MIPI2" : "MIPI"); dev_dbg(dev->dev, "h %d v %d\n", mode->hdisplay, mode->vdisplay); if (pipe == 2) { mipi_reg = MIPI_C; dspcntr_reg = DSPCCNTR; pipeconf_reg = PIPECCONF; reg_offset = MIPIC_REG_OFFSET; dspcntr_val = dev_priv->dspcntr2; pipeconf_val = dev_priv->pipeconf2; } else { mipi_val |= 0x2; /*two lanes for port A and C respectively*/ } if (!gma_power_begin(dev, true)) { dev_err(dev->dev, "hw begin failed\n"); return; } REG_WRITE(dspcntr_reg, dspcntr_val); REG_READ(dspcntr_reg); /* 20ms delay before sending exit_sleep_mode */ msleep(20); /* Send exit_sleep_mode DCS */ ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_EXIT_SLEEP_MODE, NULL, 0, CMD_DATA_SRC_SYSTEM_MEM); if (ret) { dev_err(dev->dev, "sent exit_sleep_mode faild\n"); goto out_err; } /* Send set_tear_on DCS */ ret = mdfld_dsi_dbi_send_dcs(dsi_output, DCS_SET_TEAR_ON, ¶m, 1, CMD_DATA_SRC_SYSTEM_MEM); if (ret) { dev_err(dev->dev, "%s - sent set_tear_on faild\n", __func__); goto out_err; } /* Do some init stuff */ REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR); REG_READ(pipeconf_reg); /* TODO: this looks ugly, try to move it to CRTC mode setting*/ if (pipe == 2) dev_priv->pipeconf2 |= PIPEACONF_DSR; else dev_priv->pipeconf |= PIPEACONF_DSR; dev_dbg(dev->dev, "pipeconf %x\n", REG_READ(pipeconf_reg)); ret = mdfld_dsi_dbi_update_area(dsi_output, 0, 0, h_active_area - 1, v_active_area - 1); if (ret) { dev_err(dev->dev, "update area failed\n"); goto out_err; } out_err: gma_power_end(dev); if (ret) dev_err(dev->dev, "mode set failed\n"); }