static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable) { unsigned long flag; int data; int cndx = 0; struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; mdp4_allocate_writeback_buf(mfd, MDP4_MIXER1); if (!mfd->ov1_wb_buf->write_addr) { pr_info("%s: ctrl=%d blt_base NOT assigned\n", __func__, cndx); return; } spin_lock_irqsave(&vctrl->spin_lock, flag); if (enable && pipe->ov_blt_addr == 0) { pipe->ov_blt_addr = mfd->ov1_wb_buf->write_addr; pipe->dma_blt_addr = mfd->ov1_wb_buf->read_addr; pipe->blt_cnt = 0; pipe->ov_cnt = 0; pipe->blt_dmap_done = 0; pipe->blt_ov_koff = 0; pipe->blt_ov_done = 0; mdp4_stat.blt_dtv++; vctrl->blt_change++; } else if (enable == 0 && pipe->ov_blt_addr) { pipe->ov_blt_addr = 0; pipe->dma_blt_addr = 0; vctrl->blt_change++; } pr_info("%s: enable=%d change=%d blt_addr=%x\n", __func__, enable, vctrl->blt_change, (int)pipe->ov_blt_addr); if (!vctrl->blt_change) { spin_unlock_irqrestore(&vctrl->spin_lock, flag); return; } atomic_set(&vctrl->suspend, 1); spin_unlock_irqrestore(&vctrl->spin_lock, flag); data = inpdw(MDP_BASE + DTV_BASE); data &= 0x01; if (data) /* timing generator enabled */ mdp4_dtv_wait4dmae(0); if (pipe->ov_blt_addr == 0) { MDP_OUTP(MDP_BASE + DTV_BASE, 0); /* stop dtv */ msleep(20); mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmae_xy(pipe); MDP_OUTP(MDP_BASE + DTV_BASE, 1); /* start dtv */ } atomic_set(&vctrl->suspend, 0); }
/* * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile * has enough space h * w * 3 * 2 */ static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable) { unsigned long flag; int cndx = 0; struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; long long vtime; vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0); if (mfd->ov0_wb_buf->write_addr == 0) { pr_info("%s: no blt_base assigned\n", __func__); return; } spin_lock_irqsave(&vctrl->spin_lock, flag); if (enable && pipe->ov_blt_addr == 0) { pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr; pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr; pipe->ov_cnt = 0; pipe->dmap_cnt = 0; vctrl->ov_koff = 0; vctrl->ov_done = 0; vctrl->blt_free = 0; mdp4_stat.blt_dsi_video++; vctrl->blt_change++; } else if (enable == 0 && pipe->ov_blt_addr) { pipe->ov_blt_addr = 0; pipe->dma_blt_addr = 0; vctrl->blt_free = 4; /* 4 commits to free wb buf */ vctrl->blt_change++; } pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__, vctrl->blt_change, enable, (int)pipe->ov_blt_addr); if (!vctrl->blt_change) { spin_unlock_irqrestore(&vctrl->spin_lock, flag); return; } spin_unlock_irqrestore(&vctrl->spin_lock, flag); if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) { int tg_enabled; vctrl->blt_change = 0; tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01; if (tg_enabled) { mdp4_dsi_video_wait4vsync(0, &vtime); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); mdp4_dsi_video_wait4dmap_done(0); } mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); if (tg_enabled) { /* * need wait for more than 1 ms to * make sure dsi lanes' fifo is empty and * lanes in stop state befroe reset * controller */ usleep(2000); mipi_dsi_sw_reset(); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1); } } }
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable) { unsigned long flag; int cndx = 0; struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0); if (mfd->ov0_wb_buf->write_addr == 0) { pr_info("%s: no blt_base assigned\n", __func__); return; } spin_lock_irqsave(&vctrl->spin_lock, flag); if (enable && pipe->ov_blt_addr == 0) { pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr; pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr; pipe->ov_cnt = 0; pipe->dmap_cnt = 0; vctrl->ov_koff = 0; vctrl->ov_done = 0; vctrl->blt_free = 0; mdp4_stat.blt_dsi_video++; vctrl->blt_change++; } else if (enable == 0 && pipe->ov_blt_addr) { pipe->ov_blt_addr = 0; pipe->dma_blt_addr = 0; vctrl->blt_free = 4; vctrl->blt_change++; } pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__, vctrl->blt_change, enable, (int)pipe->ov_blt_addr); if (!vctrl->blt_change) { spin_unlock_irqrestore(&vctrl->spin_lock, flag); return; } spin_unlock_irqrestore(&vctrl->spin_lock, flag); if (mdp_ov0_blt_ctl == MDP4_BLT_SWITCH_TG_OFF) { int tg_enabled; pr_debug("%s: blt enabled by switching TG off\n", __func__); tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01; if (tg_enabled) { mdp4_dsi_video_wait4dmap_done(0); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); msleep(20); } mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); if (tg_enabled) { if (pipe->ov_blt_addr) { spin_lock_irqsave(&vctrl->spin_lock, flag); pipe->ov_cnt++; vctrl->ov_koff++; mdp4_stat.kickoff_ov0++; INIT_COMPLETION(vctrl->ov_comp); vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM); outpdw(MDP_BASE + 0x0004, 0); spin_unlock_irqrestore(&vctrl->spin_lock, flag); mdp4_dsi_video_wait4ov(0); } mipi_dsi_sw_reset(); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1); } vctrl->blt_change = 0; } }
static void mdp4_dsi_cmd_do_blt(struct msm_fb_data_type *mfd, int enable) { unsigned long flags; int cndx = 0; struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; int need_wait = 0; vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0); if (mfd->ov0_wb_buf->write_addr == 0) { pr_err("%s: no blt_base assigned\n", __func__); return; } spin_lock_irqsave(&vctrl->spin_lock, flags); if (enable && pipe->ov_blt_addr == 0) { vctrl->blt_change++; if (vctrl->dmap_koff != vctrl->dmap_done) { INIT_COMPLETION(vctrl->dmap_comp); need_wait = 1; } } else if (enable == 0 && pipe->ov_blt_addr) { vctrl->blt_change++; if (vctrl->ov_koff != vctrl->dmap_done) { INIT_COMPLETION(vctrl->dmap_comp); need_wait = 1; } } spin_unlock_irqrestore(&vctrl->spin_lock, flags); if (need_wait) mdp4_dsi_cmd_wait4dmap(0); spin_lock_irqsave(&vctrl->spin_lock, flags); if (enable && pipe->ov_blt_addr == 0) { pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr; pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr; pipe->ov_cnt = 0; pipe->dmap_cnt = 0; vctrl->ov_koff = vctrl->dmap_koff; vctrl->ov_done = vctrl->dmap_done; vctrl->blt_free = 0; vctrl->blt_wait = 0; vctrl->blt_end = 0; mdp4_stat.blt_dsi_video++; } else if (enable == 0 && pipe->ov_blt_addr) { pipe->ov_blt_addr = 0; pipe->dma_blt_addr = 0; vctrl->blt_end = 1; vctrl->blt_free = 4; /* 4 commits to free wb buf */ } pr_debug("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__, vctrl->blt_change, enable, (int)pipe->ov_blt_addr); spin_unlock_irqrestore(&vctrl->spin_lock, flags); }
/* * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile * has enough space h * w * 3 * 2 */ static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable) { unsigned long flag; int data; int change = 0; mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0); if (mfd->ov0_wb_buf->phys_addr == 0) { pr_info("%s: no blt_base assigned\n", __func__); return; } spin_lock_irqsave(&mdp_spin_lock, flag); if (enable && dsi_pipe->blt_addr == 0) { dsi_pipe->blt_addr = mfd->ov0_wb_buf->phys_addr; dsi_pipe->blt_cnt = 0; dsi_pipe->ov_cnt = 0; dsi_pipe->dmap_cnt = 0; mdp4_stat.blt_dsi_video++; change++; } else if (enable == 0 && dsi_pipe->blt_addr) { dsi_pipe->blt_addr = 0; change++; } if (!change) { spin_unlock_irqrestore(&mdp_spin_lock, flag); return; } pr_debug("%s: enable=%d blt_addr=%x\n", __func__, enable, (int)dsi_pipe->blt_addr); blt_cfg_changed = 1; #if defined (LGE_BLT_LOCKUP_WR) blt_ent++; #endif spin_unlock_irqrestore(&mdp_spin_lock, flag); /* * may need mutex here to sync with whom dsiable * timing generator */ data = inpdw(MDP_BASE + DSI_VIDEO_BASE); data &= 0x01; if (data) { /* timing generator enabled */ mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE); mdp4_overlay_dsi_video_wait4event(mfd, INTR_PRIMARY_VSYNC); } #if 0 /* removed by MSM8960AAAAANLYA1049A */ if (data) { /* timing generator enabled */ if (dsi_pipe->blt_addr) { MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1); mdp4_overlay_dsi_video_prefill(mfd); mdp4_overlay_dsi_video_prefill(mfd); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); } mipi_dsi_sw_reset(); mipi_dsi_controller_cfg(1); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1); } #endif }