void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd) { mutex_lock(&mfd->dma->ov_mutex); if (mfd && mfd->panel_power_on) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_overlay_update_dsi_cmd(mfd); mdp4_dsi_cmd_kickoff_ui(mfd, dsi_pipe); mdp4_stat.kickoff_dsi++; /* signal if pan function is waiting for the update completion */ if (mfd->pan_waiting) { mfd->pan_waiting = FALSE; complete(&mfd->pan_comp); } } mdp4_overlay_resource_release(); mutex_unlock(&mfd->dma->ov_mutex); }
int mdp4_dsi_overlay_blt_start(struct msm_fb_data_type *mfd) { unsigned long flag; pr_debug("%s: blt_end=%d blt_addr=%x pid=%d\n", __func__, dsi_pipe->blt_end, (int)dsi_pipe->blt_addr, current->pid); if (dsi_pipe->blt_addr == 0) { mdp4_dsi_cmd_dma_busy_wait(mfd); spin_lock_irqsave(&mdp_spin_lock, flag); dsi_pipe->blt_end = 0; dsi_pipe->blt_cnt = 0; dsi_pipe->ov_cnt = 0; dsi_pipe->dmap_cnt = 0; dsi_pipe->blt_addr = dsi_pipe->blt_base; spin_unlock_irqrestore(&mdp_spin_lock, flag); mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); return 0; } return -EBUSY; }
static void mipi_novatek_set_backlight(struct msm_fb_data_type *mfd) { struct mipi_panel_info *mipi; static int bl_level_old; mipi = &mfd->panel_info.mipi; if (bl_level_old == mfd->bl_level) return; mutex_lock(&mfd->dma->ov_mutex); /* mdp4_dsi_cmd_busy_wait: will turn on dsi clock also */ mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); led_pwm1[1] = (unsigned char)(mfd->bl_level); mipi_dsi_cmds_tx(mfd, &novatek_tx_buf, novatek_cmd_backlight_cmds, ARRAY_SIZE(novatek_cmd_backlight_cmds)); bl_level_old = mfd->bl_level; mutex_unlock(&mfd->dma->ov_mutex); return; }
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd) { if (!mfd) return; mutex_lock(&mfd->dma->ov_mutex); if (mfd->panel_power_on) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_overlay_update_dsi_cmd(mfd); mdp4_dsi_cmd_kickoff_ui(mfd, dsi_pipe); mdp4_iommu_unmap(dsi_pipe); /* signal if pan function is waiting for the update completion */ if (mfd->pan_waiting) { mfd->pan_waiting = FALSE; complete(&mfd->pan_comp); } } mutex_unlock(&mfd->dma->ov_mutex); }
int mdp4_dsi_overlay_blt_start(struct msm_fb_data_type *mfd) { unsigned long flag; #ifdef BLTDEBUG printk("%s: blt_end=%d blt_addr=%x pid=%d\n", __func__, dsi_pipe->blt_end, (int)dsi_pipe->blt_addr, current->pid); #endif if (dsi_pipe->blt_addr == 0) { mdp4_dsi_cmd_dma_busy_wait(mfd, dsi_pipe); spin_lock_irqsave(&mdp_spin_lock, flag); dsi_pipe->blt_end = 0; dsi_pipe->blt_cnt = 0; dsi_pipe->ov_cnt = 0; dsi_pipe->dmap_cnt = 0; dsi_pipe->blt_addr = dsi_pipe->blt_base; spin_unlock_irqrestore(&mdp_spin_lock, flag); return 0; } return -EBUSY; }
/* 3D side by side */ void mdp4_dsi_cmd_3d_sbys(struct msm_fb_data_type *mfd, struct msmfb_overlay_3d *r3d) { struct fb_info *fbi; struct mdp4_overlay_pipe *pipe; int bpp; uint8 *src = NULL; if (dsi_pipe == NULL) return; dsi_pipe->is_3d = r3d->is_3d; dsi_pipe->src_height_3d = r3d->height; dsi_pipe->src_width_3d = r3d->width; pipe = dsi_pipe; if (pipe->is_3d) mdp4_overlay_panel_3d(pipe->mixer_num, MDP4_3D_SIDE_BY_SIDE); else mdp4_overlay_panel_3d(pipe->mixer_num, MDP4_3D_NONE); if (mfd->panel_power_on) mdp4_dsi_cmd_dma_busy_wait(mfd); fbi = mfd->fbi; if (pipe->is_3d) { bpp = fbi->var.bits_per_pixel / 8; pipe->src_height = pipe->src_height_3d; pipe->src_width = pipe->src_width_3d; pipe->src_h = pipe->src_height_3d; pipe->src_w = pipe->src_width_3d; pipe->dst_h = pipe->src_height_3d; pipe->dst_w = pipe->src_width_3d; pipe->srcp0_ystride = msm_fb_line_length(0, pipe->src_width, bpp); } else { /* 2D */ pipe->src_height = fbi->var.yres; pipe->src_width = fbi->var.xres; pipe->src_h = fbi->var.yres; pipe->src_w = fbi->var.xres; pipe->dst_h = fbi->var.yres; pipe->dst_w = fbi->var.xres; pipe->srcp0_ystride = fbi->fix.line_length; } pipe->src_y = 0; pipe->src_x = 0; pipe->dst_y = 0; pipe->dst_x = 0; pipe->srcp0_addr = (uint32)src; mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); mdp4_overlay_rgb_setup(pipe); mdp4_mixer_stage_up(pipe); mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); mdp4_overlay_dmap_cfg(mfd, 0); /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); }
static void mipi_oscar_set_backlight(struct msm_fb_data_type *mfd) { if(!mfd) return; if(mfd->key != MFD_KEY) return; if(mfd->panel_power_on == FALSE) return; mutex_lock(&mfd->dma->ov_mutex); if (mdp4_overlay_dsi_state_get() <= ST_DSI_SUSPEND) { mipi_dsi_turn_on_clks(); mdp4_overlay_dsi_state_set(ST_DSI_PLAYING); } mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); if(backlight_cnt == true) { mipi_set_tx_power_mode(0); mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_sleep_out, ARRAY_SIZE(oscar_sleep_out)); mipi_set_tx_power_mode(1); backlight_cnt = false; } mipi_set_tx_power_mode(0); switch(mfd->bl_level){ case 13 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_190_cmds,ARRAY_SIZE(Smart_oscar_backlight_190_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_190_cmds,ARRAY_SIZE(oscar_backlight_190_cmds)); break; case 12 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_180_cmds,ARRAY_SIZE(Smart_oscar_backlight_180_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_180_cmds,ARRAY_SIZE(oscar_backlight_180_cmds)); break; case 11 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_170_cmds,ARRAY_SIZE(Smart_oscar_backlight_170_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_170_cmds,ARRAY_SIZE(oscar_backlight_170_cmds)); break; case 10 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_160_cmds,ARRAY_SIZE(Smart_oscar_backlight_160_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_160_cmds,ARRAY_SIZE(oscar_backlight_160_cmds)); break; case 9 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_150_cmds,ARRAY_SIZE(Smart_oscar_backlight_150_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_150_cmds,ARRAY_SIZE(oscar_backlight_150_cmds)); break; case 8 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_140_cmds,ARRAY_SIZE(Smart_oscar_backlight_140_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_140_cmds,ARRAY_SIZE(oscar_backlight_140_cmds)); break; case 7 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_130_cmds,ARRAY_SIZE(Smart_oscar_backlight_130_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_130_cmds,ARRAY_SIZE(oscar_backlight_130_cmds)); break; case 6 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_120_cmds,ARRAY_SIZE(Smart_oscar_backlight_120_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_120_cmds,ARRAY_SIZE(oscar_backlight_120_cmds)); break; case 5 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_110_cmds,ARRAY_SIZE(Smart_oscar_backlight_110_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_110_cmds,ARRAY_SIZE(oscar_backlight_110_cmds)); break; case 4 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_100_cmds,ARRAY_SIZE(Smart_oscar_backlight_100_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_100_cmds,ARRAY_SIZE(oscar_backlight_100_cmds)); break; case 3 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_90_cmds,ARRAY_SIZE(Smart_oscar_backlight_90_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_90_cmds,ARRAY_SIZE(oscar_backlight_90_cmds)); break; case 2 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_80_cmds,ARRAY_SIZE(Smart_oscar_backlight_80_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_80_cmds,ARRAY_SIZE(oscar_backlight_80_cmds)); break; case 1 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_70_cmds,ARRAY_SIZE(Smart_oscar_backlight_70_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_70_cmds,ARRAY_SIZE(oscar_backlight_70_cmds)); break; case 0 : #ifdef CONFIG_F_SKYDISP_SMART_DIMMING if(chnnel_mtp) mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, Smart_oscar_backlight_70_cmds,ARRAY_SIZE(Smart_oscar_backlight_70_cmds)); else #endif mipi_dsi_cmds_tx(mfd, &oscar_tx_buf, oscar_backlight_70_cmds,ARRAY_SIZE(oscar_backlight_70_cmds)); if(backlight_control == true) backlight_cnt = true; break; } mipi_set_tx_power_mode(1); mutex_unlock(&mfd->dma->ov_mutex); if(mfd->bl_level > 0) oscar_state.backlightoff = true; else oscar_state.backlightoff = false; printk(KERN_WARNING"[%s] = %d, backlight_cnt = %d\n",__func__,mfd->bl_level,backlight_cnt); }
int mdp4_dsi_cmd_off(struct platform_device *pdev) { int ret = 0; int cndx = 0; struct msm_fb_data_type *mfd; struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; struct vsync_update *vp; int undx; pr_debug("%s+:\n", __func__); mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; if (pipe == NULL) { pr_err("%s: NO base pipe\n", __func__); return ret; } atomic_set(&vctrl->suspend, 1); atomic_set(&vctrl->vsync_resume, 0); complete_all(&vctrl->vsync_comp); /* sanity check, free pipes besides base layer */ mdp4_overlay_unset_mixer(pipe->mixer_num); mdp4_mixer_stage_down(pipe, 1); mdp4_overlay_pipe_free(pipe); vctrl->base_pipe = NULL; if (vctrl->clk_enabled) { /* * in case of suspend, vsycn_ctrl off is not * received from frame work which left clock on * then, clock need to be turned off here */ mdp_clk_ctrl(0); } undx = vctrl->update_ndx; vp = &vctrl->vlist[undx]; if (vp->update_cnt) { /* * pipe's iommu will be freed at next overlay play * and iommu_drop statistic will be increased by one */ vp->update_cnt = 0; /* empty queue */ } vctrl->clk_enabled = 0; vctrl->vsync_enabled = 0; vctrl->clk_control = 0; vctrl->expire_tick = 0; vsync_irq_disable(INTR_PRIMARY_RDPTR, MDP_PRIM_RDPTR_TERM); pr_debug("%s-:\n", __func__); /* * footswitch off * this will casue all mdp register * to be reset to default * after footswitch on later */ #if 0 // FIXME if (pdata && pdata->power_on_panel_at_pan) mdp4_dsi_cmd_dma_busy_wait(mfd); #endif return ret; }
void disp_ext_refresh_err_report_check(struct msm_fb_data_type *mfd) { struct dsi_cmd_desc dm_dsi_cmds; #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM char mipi_reg; #else char mipi_reg[2]; #endif int ret; if(err_report_chek_count < 1) { err_report_chek_count++; return; } mdp_pipe_ctrl(MDP_CMD_BLOCK,MDP_BLOCK_POWER_ON, FALSE); #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds)); mipi_reg = 0xAB; dm_dsi_cmds.dtype = DTYPE_DCS_READ; /* Command type */ dm_dsi_cmds.last = 1; /* Last command */ dm_dsi_cmds.vc = 0; /* Virtual Channel */ dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */ dm_dsi_cmds.wait = 0; /* wait response by msleep() */ dm_dsi_cmds.dlen = 1; /* Data length */ dm_dsi_cmds.payload = &mipi_reg; /* Data */ if (mdp_rev >= MDP_REV_41) { mutex_lock(&mfd->dma->ov_mutex); } else { down(&mfd->dma->mutex); } mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(); mdp4_dsi_clock_mod(); mipi_dsi_op_mode_config(DSI_CMD_MODE); /* LowSpeed */ mipi_set_tx_power_mode(1); ret = mipi_dsi_cmds_rx(mfd, &refresh_dsi_buff_tp, &refresh_dsi_buff_rp, &dm_dsi_cmds, 2); /* HighSpeed */ mipi_set_tx_power_mode(0); mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode); if (mdp_rev >= MDP_REV_41) { mutex_unlock(&mfd->dma->ov_mutex); } else { up(&mfd->dma->mutex); } #else mipi_dsi_clk_cfg(1); memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds)); mipi_reg[0] = 0xB0; mipi_reg[1] = 0x04; dm_dsi_cmds.dtype = DTYPE_GEN_WRITE2; /* Command type */ dm_dsi_cmds.last = 1; /* Last command */ dm_dsi_cmds.vc = 0; /* Virtual Channel */ dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */ dm_dsi_cmds.wait = 0; /* wait response by msleep() */ dm_dsi_cmds.dlen = 2; /* Data length */ dm_dsi_cmds.payload = mipi_reg; /* Data */ if (mdp_rev >= MDP_REV_41) { mutex_lock(&mfd->dma->ov_mutex); } else { down(&mfd->dma->mutex); } mdp4_dsi_cmd_busy(); mipi_dsi_mdp_busy_wait(); mdp4_dsi_clock_mod(); mipi_dsi_op_mode_config(DSI_CMD_MODE); mipi_set_tx_power_mode(0); mipi_dsi_cmds_tx(&refresh_dsi_buff_tp, &dm_dsi_cmds, 1); memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds)); mipi_reg[0] = 0xB5; dm_dsi_cmds.dtype = DTYPE_GEN_READ1; /* Command type */ dm_dsi_cmds.last = 1; /* Last command */ dm_dsi_cmds.vc = 0; /* Virtual Channel */ dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */ dm_dsi_cmds.wait = 0; /* wait response by msleep() */ dm_dsi_cmds.dlen = 1; /* Data length */ dm_dsi_cmds.payload = mipi_reg; /* Data */ mdp4_dsi_clock_mod(); mipi_dsi_op_mode_config(DSI_CMD_MODE); mipi_set_tx_power_mode(0); ret = mipi_dsi_cmds_rx( mfd, &refresh_dsi_buff_tp, &refresh_dsi_buff_rp, &dm_dsi_cmds, 3); if( ret == 0 || refresh_dsi_buff_rp.data[0] != 0 || refresh_dsi_buff_rp.data[1] != 0 || refresh_dsi_buff_rp.data[2] != 0 ) { disp_ext_reflesh_set_sw(1); } memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds)); mipi_reg[0] = 0x0A; dm_dsi_cmds.dtype = DTYPE_DCS_READ; /* Command type */ dm_dsi_cmds.last = 1; /* Last command */ dm_dsi_cmds.vc = 0; /* Virtual Channel */ dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */ dm_dsi_cmds.wait = 0; /* wait response by msleep() */ dm_dsi_cmds.dlen = 1; /* Data length */ dm_dsi_cmds.payload = mipi_reg; /* Data */ mdp4_dsi_clock_mod(); mipi_dsi_op_mode_config(DSI_CMD_MODE); mipi_set_tx_power_mode(1); ret = mipi_dsi_cmds_rx( mfd, &refresh_dsi_buff_tp, &refresh_dsi_buff_rp, &dm_dsi_cmds, 1); if( ret == 0 || refresh_dsi_buff_rp.data[0] != 0x1c ) { disp_ext_reflesh_set_sw(1); } memset(&dm_dsi_cmds, 0x00, sizeof(dm_dsi_cmds)); mipi_reg[0] = 0xB0; mipi_reg[1] = 0x03; dm_dsi_cmds.dtype = DTYPE_GEN_WRITE2; /* Command type */ dm_dsi_cmds.last = 1; /* Last command */ dm_dsi_cmds.vc = 0; /* Virtual Channel */ dm_dsi_cmds.ack = 1; /* Don't care, dsi_host default ON set */ dm_dsi_cmds.wait = 0; /* wait response by msleep() */ dm_dsi_cmds.dlen = 2; /* Data length */ dm_dsi_cmds.payload = mipi_reg; /* Data */ mdp4_dsi_clock_mod(); mipi_dsi_op_mode_config(DSI_CMD_MODE); mipi_set_tx_power_mode(1); mipi_dsi_cmds_tx(&refresh_dsi_buff_tp, &dm_dsi_cmds, 1); mipi_dsi_op_mode_config(mfd->panel_info.mipi.mode); if (mdp_rev >= MDP_REV_41) { mutex_unlock(&mfd->dma->ov_mutex); } else { up(&mfd->dma->mutex); } mipi_dsi_clk_cfg(0); #endif mdp_pipe_ctrl(MDP_CMD_BLOCK,MDP_BLOCK_POWER_OFF, FALSE); #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM if( ret == 0 || refresh_dsi_buff_rp.data[0] != 0 || refresh_dsi_buff_rp.data[1] != 0 ) { disp_ext_reflesh_set_sw(1); } #endif }
/*LGE_CHANGE_E LCD Reset After Data Pulled Down*/ static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ //LGE_CHANGE_S [Kiran] Change LCD sleep sequence /*LCD Reset After data pulled Down*/ #if 0 if(lglogo_firstboot) { mipi_dsi_op_mode_config(DSI_CMD_MODE); } #endif /*LGE_CHANGE_E LCD Reset After Data Pulled Down*/ //LGE_CHANGE_E [Kiran] Change LCD sleep sequence if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif /*In case of ESD no delays required in power off*/ //LGE_CHANGE_S [Kiran] Change LCD sleep sequence #ifdef CONFIG_LGE_LCD_ESD_DETECTION if (true == is_esd_occured) { printk("ESD.Paneloff ASAP\n"); } else #endif msleep(300); //LGE_CHANGE_E [Kiran] Change LCD sleep sequence #ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO if(lglogo_firstboot) { printk(KERN_INFO "[DISPLAY]::%s\n",__func__); local_bh_disable(); lglogo_mipi_dsi_clk_disable(); local_bh_enable(); } else #endif { local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); } /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); #ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO if(!lglogo_firstboot) #endif { local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); } //LGE_CHANGE_S [Kiran] Change LCD sleep sequence #if 1 /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); /*Turning off DMA_P block*/ mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); #endif //LGE_CHANGE_E [Kiran] Change LCD sleep sequence /*LCD Reset After data pulled Down*/ mipi_ldp_lcd_panel_poweroff(); /*LGE_CHANGE_E LCD Reset After Data Pulled Down*/ if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); #ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO lglogo_firstboot = FALSE; #endif return ret; }
void mdp4_dsi_cmd_3d(struct msm_fb_data_type *mfd, struct msmfb_overlay_3d *r3d) { MDPIBUF *iBuf = &mfd->ibuf; struct fb_info *fbi; struct mdp4_overlay_pipe *pipe; int bpp; uint8 *src = NULL; if (r3d->is_3d == PADDING_ENABLE || r3d->is_3d == PADDING_DISABLE) { mfd->enable_uipadding = r3d->is_3d; if (r3d->is_3d == PADDING_DISABLE) mdp4_overlay_handle_padding(mfd, false); return; } if (dsi_pipe == NULL) return; PR_DISP_INFO("%s(%d) is3d %d pid=%d\n", __func__, __LINE__, r3d->is_3d, current->pid); dsi_pipe->is_3d = r3d->is_3d; dsi_pipe->src_height_3d = r3d->height; dsi_pipe->src_width_3d = r3d->width; src = (uint8 *) iBuf->buf; pipe = dsi_pipe; #ifdef CONFIG_FB_MSM_MIPI_DSI if (mfd->panel_power_on) mdp4_dsi_cmd_dma_busy_wait(mfd, pipe); if (dsi_pipe->blt_addr) mdp4_dsi_blt_dmap_busy_wait(mfd); #endif fbi = mfd->fbi; if (pipe->is_3d) { bpp = fbi->var.bits_per_pixel / 8; pipe->src_height = pipe->src_height_3d; pipe->src_width = pipe->src_width_3d; pipe->src_h = pipe->src_height_3d; pipe->src_w = pipe->src_width_3d; pipe->dst_h = pipe->src_height_3d; pipe->dst_w = pipe->src_width_3d; pipe->srcp0_ystride = msm_fb_line_length(0, pipe->src_width, bpp); } else { /* 2D */ pipe->src_height = fbi->var.yres; pipe->src_width = fbi->var.xres; pipe->src_h = fbi->var.yres; pipe->src_w = fbi->var.xres; pipe->dst_h = fbi->var.yres; pipe->dst_w = fbi->var.xres; pipe->srcp0_ystride = fbi->fix.line_length; } pipe->src_y = 0; pipe->src_x = 0; pipe->dst_y = 0; pipe->dst_x = 0; pipe->srcp0_addr = (uint32)src; PR_DISP_DEBUG("%s(%d) is3d %d srcx %d srcy %d srcw %d srch %d dstx %d dsty %d dstw %d dsth %d ystride %d\n", __func__, __LINE__, pipe->is_3d, pipe->src_x, pipe->src_y, pipe->src_w, pipe->src_h, pipe->dst_x, pipe->dst_y, pipe->dst_w, pipe->dst_h, pipe->srcp0_ystride); mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); mdp4_overlay_rgb_setup(pipe); mdp4_mixer_stage_up(pipe); mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); mdp4_overlay_dmap_cfg(mfd, 0); mdp4_mipi_vsync_enable(mfd, pipe, 0); /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); wmb(); }
int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } else { /* video mode, wait until fifo cleaned */ mipi_dsi_controller_cfg(0); } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif #if defined(CONFIG_FB_MSM_MIPI_S6E8AA0_HD720_PANEL) || \ defined(CONFIG_FB_MSM_MIPI_S6E8AA0_WXGA_Q1_PANEL) MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x00000000); // for LCD-on when wakeup #endif local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; PR_DISP_DEBUG(" %s\n", __func__); mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else htc_mdp_sem_down(current, &mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else htc_mdp_sem_up(&mfd->dma->mutex); return ret; }
/* * DSI panel reply with MAX_RETURN_PACKET_SIZE bytes of data * plus DCS header, ECC and CRC for DCS long read response * mipi_dsi_controller only have 4x32 bits register ( 16 bytes) to * hold data per transaction. * MIPI_DSI_LEN equal to 8 * len should be either 4 or 8 * any return data more than MIPI_DSI_LEN need to be break down * to multiple transactions. * * ov_mutex need to be acquired before call this function. */ int mipi_dsi_cmds_rx(struct msm_fb_data_type *mfd, struct dsi_buf *tp, struct dsi_buf *rp, struct dsi_cmd_desc *cmds, int len) { int cnt, res; static int pkt_size; if (len <= 2) cnt = 4; /* short read */ else { if (len > MIPI_DSI_LEN) len = MIPI_DSI_LEN; /* 8 bytes at most */ res = len & 0x03; len += (4 - res); /* 4 bytes align */ /* * add extra 2 bytes to len to have overall * packet size is multipe by 4. This also make * sure 4 bytes dcs headerlocates within a * 32 bits register after shift in. * after all, len should be either 6 or 10. */ len += 2; cnt = len + 6; /* 4 bytes header + 2 bytes crc */ } if (mfd->panel_info.type == MIPI_CMD_PANEL) { /* make sure mdp dma is not txing pixel data */ mdp4_dsi_cmd_dma_busy_wait(mfd); } mipi_dsi_enable_irq(); if (pkt_size != len) { /* set new max pkt size */ pkt_size = len; max_pktsize[0] = pkt_size; mipi_dsi_buf_init(tp); mipi_dsi_cmd_dma_add(tp, pkt_size_cmd); mipi_dsi_cmd_dma_tx(tp); } mipi_dsi_buf_init(tp); mipi_dsi_cmd_dma_add(tp, cmds); /* transmit read comamnd to client */ mipi_dsi_cmd_dma_tx(tp); /* * once cmd_dma_done interrupt received, * return data from client is ready and stored * at RDBK_DATA register already */ mipi_dsi_cmd_dma_rx(rp, cnt); mipi_dsi_disable_irq(); /* strip off dcs header & crc */ if (cnt > 4) { /* long response */ rp->data += 4; /* skip dcs header */ rp->len -= 6; /* deduct 4 bytes header + 2 bytes crc */ rp->len -= 2; /* extra 2 bytes added */ } else { rp->data += 1; /* skip dcs short header */ rp->len -= 2; /* deduct 1 byte header + 1 byte ecc */ } return rp->len; }
int disp_ext_blc_mode_select( uint8_t mode ) { struct msm_fb_data_type *mfd; DISP_LOCAL_LOG_EMERG("DISP mipi_novatek_wxga_cabc_mode_select mode=%d S\n",mode); #ifdef CONFIG_DISP_EXT_UTIL disp_ext_util_mipitx_lock(); disp_ext_util_disp_local_lock(); #endif /* CONFIG_DISP_EXT_UTIL */ if( disp_ext_util_get_disp_state() != LOCAL_DISPLAY_ON ) { #ifdef CONFIG_DISP_EXT_UTIL disp_ext_util_disp_local_unlock(); disp_ext_util_mipitx_unlock(); #endif /* CONFIG_DISP_EXT_UTIL */ pr_err("%s:panel off\n", __func__); return -1; } if( mode > 0x01 ) { #ifdef CONFIG_DISP_EXT_UTIL disp_ext_util_disp_local_unlock(); disp_ext_util_mipitx_unlock(); #endif /* CONFIG_DISP_EXT_UTIL */ pr_err("%s:parameter err\n", __func__); return -1; } if( select_mode_ctrl == mode ) { #ifdef CONFIG_DISP_EXT_UTIL disp_ext_util_disp_local_unlock(); disp_ext_util_mipitx_unlock(); #endif /* CONFIG_DISP_EXT_UTIL */ DISP_LOCAL_LOG_EMERG("%s:Request a double. state=%d,req=%d\n",__func__,select_mode_ctrl,mode); return 0; } #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM mfd = mipi_novatek_wxga_get_mfd(); #else mfd = mipi_renesas_cm_get_mfd(); #endif if( mfd == NULL ) { #ifdef CONFIG_DISP_EXT_UTIL disp_ext_util_disp_local_unlock(); disp_ext_util_mipitx_unlock(); #endif /* CONFIG_DISP_EXT_UTIL */ pr_err("%s:mfd == NULL\n", __func__); return -1; } select_mode_ctrl=mode; msm_fb_pan_lock(); msm_fb_ioctl_ppp_lock(); msm_fb_ioctl_lut_lock(); #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); #else mdp4_dsi_cmd_busy(); mipi_dsi_mdp_busy_wait(); #endif if( mode == 0 ) { #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM cabc_change[1] = 0; #else cabc_mode_select_cmds = renesas_cm_blc_off_cmds; cabc_mode_select_cmds_size = ARRAY_SIZE(renesas_cm_blc_off_cmds); #endif } else { #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM cabc_change[1] = select_mode; #else cabc_mode_select_cmds = renesas_cm_blc_on_cmds; cabc_mode_select_cmds_size = ARRAY_SIZE(renesas_cm_blc_on_cmds); #endif } #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM pr_debug("%s:cabc_change[%d,%d]\n", __func__,cabc_change[0],cabc_change[1]); DISP_LOCAL_LOG_EMERG("%s:cabc_change[%d,%d]\n", __func__,cabc_change[0],cabc_change[1]); #endif #ifndef CONFIG_FB_MSM_MIPI_DSI_RENESAS_CM mipi_dsi_cmds_tx(mfd, &disp_ext_blc_tx_buf, cabc_mode_select_cmds, ARRAY_SIZE(cabc_mode_select_cmds)); #else mipi_set_tx_power_mode(0); mipi_dsi_clk_cfg(1); mipi_dsi_cmds_tx(&disp_ext_blc_tx_buf, cabc_mode_select_cmds, cabc_mode_select_cmds_size); mipi_dsi_clk_cfg(0); #endif udelay(1); msm_fb_ioctl_lut_unlock(); msm_fb_ioctl_ppp_unlock(); msm_fb_pan_unlock(); #ifdef CONFIG_DISP_EXT_UTIL disp_ext_util_disp_local_unlock(); disp_ext_util_mipitx_unlock(); #endif /* CONFIG_DISP_EXT_UTIL */ pr_debug("%s:cabc select\n", __func__); DISP_LOCAL_LOG_EMERG("DISP mipi_novatek_wxga_cabc_mode_select E\n"); return 0; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; //#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) #if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) struct mipi_panel_info *mipi; #endif mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); //#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) #if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) mipi = &mfd->panel_info.mipi; if (mipi->force_clk_lane_hs) { u32 tmp; tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8); tmp &= ~(1<<28); MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp); wmb(); printk("[MIPI: shinbrad Low speed Clk Set(Off Sequence) .................................................]\n"); } #endif /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } else { /* video mode, wait until fifo cleaned */ #if !defined(CONFIG_MACH_MSM8960_MAGNUS) mipi_dsi_controller_cfg(0); #endif } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ #if defined (CONFIG_MACH_MSM8960_MAGNUS) ret = panel_next_off(pdev); mipi_dsi_controller_cfg(0); #else mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #endif #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; #ifdef CONFIG_HUAWEI_KERNEL struct mipi_panel_info *mipi; unsigned int datamask = 0; #endif mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_HUAWEI_KERNEL mipi = &mfd->panel_info.mipi; if (mipi->data_lane3) datamask |= 1<<3; if (mipi->data_lane2) datamask |= 1<<2; if (mipi->data_lane1) datamask |= 1<<1; if (mipi->data_lane0) datamask |= 1<<0; MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask ); mdelay(1); MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask|(1<<4)); mdelay(1); #endif #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
static int mipi_samsung_disp_send_cmd(struct msm_fb_data_type *mfd, enum mipi_samsung_cmd_list cmd, unsigned char lock) { struct dsi_cmd_desc *cmd_desc; int cmd_size = 0; wake_lock(&idle_wake_lock); if (lock) mutex_lock(&mfd->dma->ov_mutex); switch (cmd) { #ifdef CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT case PANEL_READY_TO_ON_FAST: if (Is_4_65LCD_cmc() || Is_4_65LCD_bypass()) { /*4.65 LCD_ID*/ pr_info("Select 4.65 = %x\n", LCD_Get_Value()); cmd_desc = msd.mpd->ready_to_on_fast.cmd; cmd_size = msd.mpd->ready_to_on_fast.size; } else { pr_info("Select 4.8 = %x\n", LCD_Get_Value()); cmd_desc = msd.mpd->ready_to_on_4_8_fast.cmd; cmd_size = msd.mpd->ready_to_on_4_8_fast.size; } break; #endif case PANEL_READY_TO_ON: #ifdef CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT if (Is_4_65LCD_cmc() || Is_4_65LCD_bypass()) { /*4.65 LCD_ID*/ pr_info("Select 4.65 = %x(%x)\n", LCD_Get_Value(), bypass_LCD_Id()); cmd_desc = msd.mpd->ready_to_on.cmd; cmd_size = msd.mpd->ready_to_on.size; } else { /* 4.8 LCD_ID*/ pr_info("Select 4.8 = %x(%x)\n", LCD_Get_Value(), bypass_LCD_Id()); cmd_desc = msd.mpd->ready_to_on_4_8.cmd; cmd_size = msd.mpd->ready_to_on_4_8.size; } #else cmd_desc = msd.mpd->ready_to_on.cmd; cmd_size = msd.mpd->ready_to_on.size; #endif break; case PANEL_READY_TO_OFF: cmd_desc = msd.mpd->ready_to_off.cmd; cmd_size = msd.mpd->ready_to_off.size; break; case PANEL_ON: cmd_desc = msd.mpd->on.cmd; cmd_size = msd.mpd->on.size; break; case PANEL_OFF: cmd_desc = msd.mpd->off.cmd; cmd_size = msd.mpd->off.size; break; case PANEL_LATE_ON: cmd_desc = msd.mpd->late_on.cmd; cmd_size = msd.mpd->late_on.size; break; case PANEL_EARLY_OFF: cmd_desc = msd.mpd->early_off.cmd; cmd_size = msd.mpd->early_off.size; break; case PANEL_GAMMA_UPDATE: cmd_desc = msd.mpd->gamma_update.cmd; cmd_size = msd.mpd->gamma_update.size; break; case MTP_READ_ENABLE: cmd_desc = msd.mpd->mtp_read_enable.cmd; cmd_size = msd.mpd->mtp_read_enable.size; break; #ifdef USE_ACL case PANEL_ACL_ON: cmd_desc = msd.mpd->acl_on.cmd; cmd_size = msd.mpd->acl_on.size; msd.mpd->ldi_acl_stat = true; break; case PANEL_ACL_OFF: cmd_desc = msd.mpd->acl_off.cmd; cmd_size = msd.mpd->acl_off.size; msd.mpd->ldi_acl_stat = false; break; case PANEL_ACL_UPDATE: cmd_desc = msd.mpd->acl_update.cmd; cmd_size = msd.mpd->acl_update.size; break; #endif #ifdef USE_ELVSS case PANEL_ELVSS_UPDATE: #ifdef CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT if (Is_4_65LCD_cmc() || Is_4_65LCD_bypass()) { /*4.65 LCD_ID*/ msd.mpd->set_elvss(mfd->bl_level); cmd_desc = msd.mpd->elvss_update.cmd; cmd_size = msd.mpd->elvss_update.size; } else { /* 4.8 LCD_ID*/ msd.mpd->set_elvss_4_8(mfd->bl_level); cmd_desc = msd.mpd->elvss_update_4_8.cmd; cmd_size = msd.mpd->elvss_update_4_8.size; } #else msd.mpd->set_elvss(mfd->bl_level); cmd_desc = msd.mpd->elvss_update.cmd; cmd_size = msd.mpd->elvss_update.size; #endif break; #endif #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT) \ || defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_WVGA_PT) case PANEL_BRIGHT_CTRL: cmd_desc = msd.mpd->combined_ctrl.cmd; cmd_size = msd.mpd->combined_ctrl.size; break; #endif default: goto unknown_command; ; } if (!cmd_size) goto unknown_command; if (lock) { /* mdp4_dsi_cmd_busy_wait: will turn on dsi clock also */ mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); /* Added to resolved cmd loss during dimming factory test */ mdelay(1); mipi_dsi_cmds_tx(mfd, &msd.samsung_tx_buf, cmd_desc, cmd_size); mutex_unlock(&mfd->dma->ov_mutex); } else { /* mdp4_dsi_cmd_busy_wait: will turn on dsi clock also */ mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); /* Added to resolved cmd loss during dimming factory test */ mdelay(1); mipi_dsi_cmds_tx(mfd, &msd.samsung_tx_buf, cmd_desc, cmd_size); } wake_unlock(&idle_wake_lock); return 0; unknown_command: if (lock) mutex_unlock(&mfd->dma->ov_mutex); wake_unlock(&idle_wake_lock); return 0; }