int mdp4_dsi_video_splash_done(void)
{
struct vsycn_ctrl *vctrl;
int cndx = 0;
vctrl = &vsync_ctrl_db[cndx];
mdp4_dsi_video_tg_off(vctrl);
mipi_dsi_controller_cfg(0);
return 0;
}
int mdp4_dsi_video_splash_done(struct platform_device *pdev)
{
struct vsycn_ctrl *vctrl;
int cndx = 0;
/* Turn off panel to avoid fading */
mipi_dsi_panel_power_en(pdev, 0);
vctrl = &vsync_ctrl_db[cndx];
mdp4_dsi_video_tg_off(vctrl);
mipi_dsi_controller_cfg(0);
return 0;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int mixer = 0;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_dsi_video_wait4vsync(cndx);
if (pipe == NULL)
return -EINVAL;
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
dsi_video_enabled = 0;
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_video_pipe_clean(vp);
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mixer = pipe->mixer_num;
mdp4_overlay_unset_mixer(mixer);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
mdp4_dsi_video_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
mdp4_video_vsync_irq_ctrl(cndx, 0);
}
/*
* clean up ion freelist
* there need two stage to empty ion free list
* therefore need call unmap freelist twice
*/
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp4_overlay_iommu_unmap_freelist(mixer);
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}
int mdp4_dsi_video_on(struct platform_device *pdev)
{
int dsi_width;
int dsi_height;
int dsi_bpp;
int dsi_border_clr;
int dsi_underflow_clr;
int dsi_hsync_skew;
int hsync_period;
int hsync_ctrl;
int vsync_period;
int display_hctl;
int display_v_start;
int display_v_end;
int active_hctl;
int active_h_start;
int active_h_end;
int active_v_start;
int active_v_end;
int ctrl_polarity;
int h_back_porch;
int h_front_porch;
int v_back_porch;
int v_front_porch;
int hsync_pulse_width;
int vsync_pulse_width;
int hsync_polarity;
int vsync_polarity;
int data_en_polarity;
int hsync_start_x;
int hsync_end_x;
uint8 *buf;
unsigned int buf_offset;
int bpp, ptype;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct msm_fb_data_type *mfd;
struct mdp4_overlay_pipe *pipe;
int ret = 0;
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct msm_panel_info *pinfo;
vctrl = &vsync_ctrl_db[cndx];
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
pinfo = &mfd->panel_info;
if (!mfd)
return -ENODEV;
if (mfd->key != MFD_KEY)
return -EINVAL;
mutex_lock(&mfd->dma->ov_mutex);
vctrl->mfd = mfd;
vctrl->dev = mfd->fbi->dev;
vctrl->blt_ctrl = pinfo->lcd.blt_ctrl;
vctrl->vsync_irq_enabled = 0;
vsync_irq_cnt = 0;
/* mdp clock on */
mdp_clk_ctrl(1);
fbi = mfd->fbi;
var = &fbi->var;
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf_offset = calc_fb_offset(mfd, fbi, bpp);
if (vctrl->base_pipe == NULL) {
ptype = mdp4_overlay_format2type(mfd->fb_imgType);
if (ptype < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
if (pipe == NULL) {
printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return -EBUSY;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = mfd->fb_imgType;
mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_DSI_VIDEO);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
printk(KERN_INFO "%s: format2type failed\n", __func__);
pipe->ov_blt_addr = 0;
pipe->dma_blt_addr = 0;
vctrl->base_pipe = pipe; /* keep it */
mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
} else {
pipe = vctrl->base_pipe;
}
atomic_set(&vctrl->suspend, 0);
if (!(mfd->cont_splash_done)) {
mfd->cont_splash_done = 1;
mdp4_dsi_video_tg_off(vctrl);
mipi_dsi_controller_cfg(0);
/* Clks are enabled in probe.
Disabling clocks now */
mdp_clk_ctrl(0);
}
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
pipe->bpp = bpp;
if (mfd->display_iova)
pipe->srcp0_addr = mfd->display_iova + buf_offset;
else
pipe->srcp0_addr = (uint32)(buf + buf_offset);
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
mdp4_overlay_solidfill_init(pipe);
mdp4_overlay_mdp_pipe_req(pipe, mfd);
mdp4_calc_blt_mdp_bw(mfd, pipe);
mdp4_overlay_dmap_xy(pipe); /* dma_p */
mdp4_overlay_dmap_cfg(mfd, 1);
mdp4_overlay_rgb_setup(pipe);
mdp4_overlayproc_cfg(pipe);
mdp4_overlay_reg_flush(pipe, 1);
mdp4_mixer_stage_up(pipe, 0);
mdp4_mixer_stage_commit(pipe->mixer_num);
/*
* DSI timing setting
*/
h_back_porch = var->left_margin;
h_front_porch = var->right_margin;
v_back_porch = var->upper_margin;
v_front_porch = var->lower_margin;
hsync_pulse_width = var->hsync_len;
vsync_pulse_width = var->vsync_len;
dsi_border_clr = mfd->panel_info.lcdc.border_clr;
dsi_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
dsi_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
dsi_width = mfd->panel_info.xres +
mfd->panel_info.lcdc.xres_pad;
dsi_height = mfd->panel_info.yres +
mfd->panel_info.lcdc.yres_pad;
dsi_bpp = mfd->panel_info.bpp;
hsync_period = hsync_pulse_width + h_back_porch + dsi_width
+ h_front_porch;
hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
hsync_start_x = h_back_porch + hsync_pulse_width;
hsync_end_x = hsync_period - h_front_porch - 1;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
vsync_period =
(vsync_pulse_width + v_back_porch + dsi_height + v_front_porch);
display_v_start = ((vsync_pulse_width + v_back_porch) * hsync_period)
+ dsi_hsync_skew;
display_v_end =
((vsync_period - v_front_porch) * hsync_period) + dsi_hsync_skew - 1;
if (dsi_width != var->xres) {
active_h_start = hsync_start_x + first_pixel_start_x;
active_h_end = active_h_start + var->xres - 1;
active_hctl =
ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
} else {
active_hctl = 0;
}
if (dsi_height != var->yres) {
active_v_start =
display_v_start + first_pixel_start_y * hsync_period;
active_v_end = active_v_start + (var->yres) * hsync_period - 1;
active_v_start |= ACTIVE_START_Y_EN;
} else {
active_v_start = 0;
active_v_end = 0;
}
dsi_underflow_clr |= 0x80000000; /* enable recovery */
hsync_polarity = 0;
vsync_polarity = 0;
data_en_polarity = 0;
ctrl_polarity =
(data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x4, hsync_ctrl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x8, vsync_period * hsync_period);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0xc,
vsync_pulse_width * hsync_period);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x10, display_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x14, display_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x18, display_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x1c, active_hctl);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x20, active_v_start);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x24, active_v_end);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x28, dsi_border_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x2c, dsi_underflow_clr);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x30, dsi_hsync_skew);
MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x38, ctrl_polarity);
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
mdp_histogram_ctrl_all(TRUE);
// mdp4_overlay_dsi_video_start();
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_dsi_video_wait4vsync(cndx);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
dsi_video_enabled = 0;
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
}
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
vp->update_cnt = 0; /* empty queue */
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
mdp4_dsi_video_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
vsync_irq_disable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
}
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
return ret;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int undx, need_wait = 0;
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_dsi_video_wait4vsync(cndx);
atomic_set(&vctrl->vsync_resume, 0);
complete_all(&vctrl->vsync_comp);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
dsi_video_enabled = 0;
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_video_pipe_clean(vp);
}
/* MM-KW-TraceLog-00+ */
printk(KERN_INFO "[DISPLAY]%s: pipe %d, cnt %d, e %d\n",
__func__, (pipe != NULL), mfd->ref_cnt, vctrl->vsync_irq_enabled);
if (pipe) {
/* sanity check, free pipes besides base layer */
mdp4_overlay_unset_mixer(pipe->mixer_num);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
mdp4_dsi_video_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
return ret;
}
int mdp4_dsi_video_off(struct platform_device *pdev)
{
int ret = 0;
int cndx = 0;
struct msm_fb_data_type *mfd;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
struct vsync_update *vp;
unsigned long flags;
int mixer = 0;
int undx, need_wait = 0;
#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_HD_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT_PANEL) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WUXGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WUXGA_INVERSE_PT)
int retry_cnt = 0;
#endif
printk(KERN_INFO "%s is started.. \n", __func__);
#if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_HD_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_FHD_INVERSE_PT_PANEL) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WUXGA_PT) \
|| defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WUXGA_INVERSE_PT)
do {
ret = mipi_lgit_lcd_off(pdev);
if (ret < 0) {
panel_next_off(pdev);
msleep(2);
panel_next_on(pdev);
msleep(5);
retry_cnt++;
}
else
{ // if upper routine is successed, need to initialize ret variable.
ret = 0;
break;
}
} while(retry_cnt < 10);
printk(KERN_INFO "%s : mipi_lgit_lcd_off retry_cnt = %d\n", __func__, retry_cnt);
#endif
mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
mdp4_dsi_video_wait4vsync(cndx);
if (pipe->ov_blt_addr) {
spin_lock_irqsave(&vctrl->spin_lock, flags);
if (vctrl->ov_koff != vctrl->ov_done)
need_wait = 1;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (need_wait)
mdp4_dsi_video_wait4ov(0);
}
mdp_histogram_ctrl_all(FALSE);
dsi_video_enabled = 0;
undx = vctrl->update_ndx;
vp = &vctrl->vlist[undx];
if (vp->update_cnt) {
/*
* pipe's iommu will be freed at next overlay play
* and iommu_drop statistic will be increased by one
*/
pr_warn("%s: update_cnt=%d\n", __func__, vp->update_cnt);
mdp4_dsi_video_pipe_clean(vp);
}
if (pipe) {
/* sanity check, free pipes besides base layer */
mixer = pipe->mixer_num;
mdp4_overlay_unset_mixer(mixer);
if (mfd->ref_cnt == 0) {
/* adb stop */
if (pipe->pipe_type == OVERLAY_TYPE_BF)
mdp4_overlay_borderfill_stage_down(pipe);
/* base pipe may change after borderfill_stage_down */
pipe = vctrl->base_pipe;
mdp4_mixer_stage_down(pipe, 1);
mdp4_overlay_pipe_free(pipe, 1);
vctrl->base_pipe = NULL;
} else {
/* system suspending */
mdp4_mixer_stage_down(vctrl->base_pipe, 1);
mdp4_overlay_iommu_pipe_free(
vctrl->base_pipe->pipe_ndx, 1);
}
}
mdp4_dsi_video_tg_off(vctrl);
atomic_set(&vctrl->suspend, 1);
if (vctrl->vsync_irq_enabled) {
vctrl->vsync_irq_enabled = 0;
mdp4_video_vsync_irq_ctrl(cndx, 0);
}
/*
* clean up ion freelist
* there need two stage to empty ion free list
* therefore need call unmap freelist twice
*/
mdp4_overlay_iommu_unmap_freelist(mixer);
mdp4_overlay_iommu_unmap_freelist(mixer);
/* mdp clock off */
mdp_clk_ctrl(0);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
printk(KERN_INFO "%s is ended.. \n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return ret;
}