void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();

	if (mdp_hw_revision == MDP4_REVISION_V2_1) {
		if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_UNSET)) {
			uint32  data;
			data = inpdw(MDP_BASE + 0x0028);
			data &= ~0x0300;        /* bit 8, 9, MASTER4 */
			if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
				data |= 0x0200;
			else
				data |= 0x0100;
			MDP_OUTP(MDP_BASE + 0x00028, data);
			mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_UNSET,
				false);
		}
		if (mdp4_overlay_status_read(MDP4_OVERLAY_TYPE_SET)) {
			uint32  data;
			data = inpdw(MDP_BASE + 0x0028);
			data &= ~0x0300;        /* bit 8, 9, MASTER4 */
			MDP_OUTP(MDP_BASE + 0x00028, data);
			mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, false);
		}
	}
	mdp_enable_irq(MDP_OVERLAY0_TERM);
	mfd->dma->busy = TRUE;
	/* start OVERLAY pipe */
	mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
	unsigned long flag;


	/* change mdp clk */
	mdp4_set_perf_level();

	mipi_dsi_mdp_busy_wait(mfd);

	if (dsi_pipe->blt_addr == 0)
		mipi_dsi_cmd_mdp_start();

	mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);

	spin_lock_irqsave(&mdp_spin_lock, flag);
	mdp_enable_irq(MDP_OVERLAY0_TERM);
	mfd->dma->busy = TRUE;
	if (dsi_pipe->blt_addr)
		mfd->dma->dmap_busy = TRUE;
	/* start OVERLAY pipe */
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
	mdp4_stat.kickoff_ov0++;
}
示例#3
0
void mdp4_mddi_dma_s_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
/* use dma_s pipe ,change bpp into 24 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
	if(24 != mfd->panel_info.bpp)
	{
		mdp4_switch_bpp_config(mfd,24);	
	}
#endif
	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();

	mdp_enable_irq(MDP_DMA_S_TERM);

	if (mddi_pipe->blt_addr == 0)
		mfd->dma->busy = TRUE;

	mfd->ibuf_flushed = TRUE;
	/* start dma_s pipe */
	mdp_pipe_kickoff(MDP_DMA_S_TERM, mfd);
	mdp4_stat.kickoff_dmas++;

	/* wait until DMA finishes the current job */
#ifdef CONFIG_HUAWEI_KERNEL
    /* huawei modify */
	wait_for_completion_interruptible_timeout(&mfd->dma->comp, 2 * HZ);
#else
	wait_for_completion(&mfd->dma->comp);
#endif
	mdp_disable_irq(MDP_DMA_S_TERM);
}
void mdp4_overlay_lcdc_vsync_push(struct msm_fb_data_type *mfd,
			struct mdp4_overlay_pipe *pipe)
{
	unsigned long flag;

	if (pipe->flags & MDP_OV_PLAY_NOWAIT)
		return;

	if (lcdc_pipe->blt_addr) {
		mdp4_overlay_lcdc_dma_busy_wait(mfd);

		mdp4_lcdc_blt_ov_update(lcdc_pipe);
		lcdc_pipe->ov_cnt++;

		spin_lock_irqsave(&mdp_spin_lock, flag);
		outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
		mdp_intr_mask |= INTR_OVERLAY0_DONE;
		outp32(MDP_INTR_ENABLE, mdp_intr_mask);
		mdp_enable_irq(MDP_OVERLAY0_TERM);
		mfd->dma->busy = TRUE;
		mb();	/* make sure all registers updated */
		spin_unlock_irqrestore(&mdp_spin_lock, flag);
		outpdw(MDP_BASE + 0x0004, 0); /* kickoff overlay engine */
		mdp4_stat.kickoff_ov0++;
		mb();
		mdp4_overlay_lcdc_wait4event(mfd, INTR_DMA_P_DONE);
	} else {
		mdp4_overlay_lcdc_wait4event(mfd, INTR_PRIMARY_VSYNC);
	}
	mdp4_set_perf_level();
}
示例#5
0
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
	unsigned long flag;

/* use dma_p(overlay) pipe ,change bpp into 16 */
#ifdef CONFIG_FB_MSM_BPP_SWITCH
	if(16 != mfd->panel_info.bpp)
	{
		mdp4_switch_bpp_config(mfd,16);	
	}
#endif

	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();

	mdp_enable_irq(MDP_OVERLAY0_TERM);
	spin_lock_irqsave(&mdp_spin_lock, flag);
	mfd->dma->busy = TRUE;
	if (mddi_pipe->blt_addr)
		mfd->dma->dmap_busy = TRUE;
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	/* start OVERLAY pipe */
	mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
	mdp4_stat.kickoff_ov0++;
}
示例#6
0
void mdp4_overlay_dtv_wait_for_ov(struct msm_fb_data_type *mfd,
	struct mdp4_overlay_pipe *pipe)
{
	if (mfd->ov_end) {
		mfd->ov_end = false;
		return;
	}
	mdp4_overlay_dtv_wait4_ov_done(mfd, pipe);
	mdp4_set_perf_level();
}
示例#7
0
void mdp4_overlay_lcdc_vsync_push(struct msm_fb_data_type *mfd,
			struct mdp4_overlay_pipe *pipe)
{
	if (pipe->flags & MDP_OV_PLAY_NOWAIT)
		return;

	mdp4_overlay_lcdc_wait4event(mfd, 1);

	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();
}
示例#8
0
void mdp4_atv_overlay(struct msm_fb_data_type *mfd)
{
	struct fb_info *fbi = mfd->fbi;
	uint8 *buf;
	unsigned int buf_offset;
	int bpp;
	unsigned long flag;
	struct mdp4_overlay_pipe *pipe;

	if (!mfd->panel_power_on)
		return;

	/* no need to power on cmd block since it's lcdc mode */
	bpp = fbi->var.bits_per_pixel / 8;
	buf = (uint8 *) fbi->fix.smem_start;
	buf_offset = calc_fb_offset(mfd, fbi, bpp);

	mutex_lock(&mfd->dma->ov_mutex);

	pipe = atv_pipe;
	if (mfd->map_buffer) {
		pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \
			buf_offset;
		pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd->
			map_buffer->iova[0], pipe->srcp0_addr);
	} else {
		pipe->srcp0_addr = (uint32)(buf + buf_offset);
	}
	mdp4_overlay_rgb_setup(pipe);
	mdp4_mixer_stage_up(pipe);
#ifdef QCT_PATCH
	mdp4_overlay_reg_flush(pipe, 0);
#endif
	printk(KERN_INFO "mdp4_atv_overlay: pipe=%x ndx=%d\n",
					(int)pipe, pipe->pipe_ndx);

	/* enable irq */
	spin_lock_irqsave(&mdp_spin_lock, flag);
	mdp_enable_irq(MDP_OVERLAY1_TERM);
	INIT_COMPLETION(atv_pipe->comp);
	mfd->dma->waiting = TRUE;
	outp32(MDP_INTR_CLEAR, INTR_OVERLAY1_DONE);
	mdp_intr_mask |= INTR_OVERLAY1_DONE;
	outp32(MDP_INTR_ENABLE, mdp_intr_mask);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	wait_for_completion_killable(&atv_pipe->comp);
	mdp_disable_irq(MDP_OVERLAY1_TERM);

	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();

	mdp4_stat.kickoff_atv++;
	mutex_unlock(&mfd->dma->ov_mutex);
}
示例#9
0
void mdp4_overlay_dtv_ov_done_push(struct msm_fb_data_type *mfd,
                                   struct mdp4_overlay_pipe *pipe)
{
    mdp4_overlay_dtv_ov_start(mfd);
    if (pipe->flags & MDP_OV_PLAY_NOWAIT)
        return;

    mdp4_overlay_dtv_wait4_ov_done(mfd, pipe);

    /* change mdp clk while mdp is idle` */
    mdp4_set_perf_level();
}
示例#10
0
void mdp4_overlay_dtv_vsync_push(struct msm_fb_data_type *mfd,
			struct mdp4_overlay_pipe *pipe)
{

	mdp4_overlay_reg_flush(pipe, 1);
	if (pipe->flags & MDP_OV_PLAY_NOWAIT)
		return;

	mdp4_overlay_dtv_wait4vsync(mfd);

	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
                                  struct mdp4_overlay_pipe *pipe)
{
    unsigned long flag;

    mdp4_iommu_attach();
    /* change mdp clk */
    mdp4_set_perf_level();

    mipi_dsi_mdp_busy_wait(mfd);

    mipi_dsi_cmd_mdp_start();

    mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);

    /* MDP cmd block enable */
    mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);

    spin_lock_irqsave(&mdp_spin_lock, flag);
    outp32(MDP_INTR_CLEAR, INTR_DMA_P_DONE);
    outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
    mdp_intr_mask |= INTR_DMA_P_DONE;
    if (dsi_pipe && dsi_pipe->ov_blt_addr) {
        mdp_intr_mask |= INTR_OVERLAY0_DONE;
        mfd->dma->busy = TRUE;
    } else
        mdp_intr_mask &= ~INTR_OVERLAY0_DONE;
    mfd->dma->dmap_busy = TRUE;
    outp32(MDP_INTR_ENABLE, mdp_intr_mask);
    mdp_enable_irq(MDP_DMA2_TERM);
    wmb();
    spin_unlock_irqrestore(&mdp_spin_lock, flag);

    /* MDP cmd block disable */
    mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

    mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
    wmb();
    mdp4_stat.kickoff_ov0++;
    dsi_pipe->ov_cnt++;
    if (dsi_pipe && dsi_pipe->ov_blt_addr) {
        wmb();
        outpdw(MDP_BASE + 0x000c, 0x0);
        mdp4_stat.kickoff_dmap++;
        wmb();
        dsi_pipe->dmap_cnt++;
        dsi_pipe->blt_cnt++;
    }
}
void mdp4_mddi_dma_s_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();

	mdp_enable_irq(MDP_DMA_S_TERM);
	mfd->dma->busy = TRUE;
	mfd->ibuf_flushed = TRUE;
	/* start dma_s pipe */
	mdp_pipe_kickoff(MDP_DMA_S_TERM, mfd);

	/* wait until DMA finishes the current job */
	wait_for_completion(&mfd->dma->comp);
	mdp_disable_irq(MDP_DMA_S_TERM);
}
void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
	unsigned long flag;
	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();

	mdp_enable_irq(MDP_OVERLAY0_TERM);
	spin_lock_irqsave(&mdp_spin_lock, flag);
	mfd->dma->busy = TRUE;
	if (mddi_pipe->blt_addr)
		mfd->dma->dmap_busy = TRUE;
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	/* start OVERLAY pipe */
	mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
	mdp4_stat.kickoff_ov0++;
}
void mdp4_atv_overlay(struct msm_fb_data_type *mfd)
{
	struct fb_info *fbi = mfd->fbi;
	uint8 *buf;
	int bpp;
	unsigned long flag;
	struct mdp4_overlay_pipe *pipe;

	if (!mfd->panel_power_on)
		return;

	/* no need to power on cmd block since it's lcdc mode */
	bpp = fbi->var.bits_per_pixel / 8;
	buf = (uint8 *) fbi->fix.smem_start;
	buf += fbi->var.xoffset * bpp +
		fbi->var.yoffset * fbi->fix.line_length;

	mutex_lock(&mfd->dma->ov_mutex);

	pipe = atv_pipe;
	pipe->srcp0_addr = (uint32) buf;
	mdp4_overlay_rgb_setup(pipe);
	mdp4_overlay_reg_flush(pipe, 1); /* rgb2 and mixer1 */

	printk(KERN_INFO "mdp4_atv_overlay: pipe=%x ndx=%d\n",
					(int)pipe, pipe->pipe_ndx);

	/* enable irq */
	spin_lock_irqsave(&mdp_spin_lock, flag);
	mdp_enable_irq(MDP_OVERLAY1_TERM);
	INIT_COMPLETION(atv_pipe->comp);
	mfd->dma->waiting = TRUE;
	outp32(MDP_INTR_CLEAR, INTR_OVERLAY1_DONE);
	mdp_intr_mask |= INTR_OVERLAY1_DONE;
	outp32(MDP_INTR_ENABLE, mdp_intr_mask);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	wait_for_completion_killable(&atv_pipe->comp);
	mdp_disable_irq(MDP_OVERLAY1_TERM);

	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();

	mdp4_stat.kickoff_atv++;
	mutex_unlock(&mfd->dma->ov_mutex);
}
示例#15
0
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
	unsigned long flag, rflag;

#ifdef FACTORY_TEST
	if (!is_lcd_connected)
		return;
#endif
/*
*QCT_PATCH-sbyun to avoid confilt
*between on going video image and new overlay image,
*add some delay when mdp of dma is in busy status
*/
	/* change mdp clk */
	mdp4_set_perf_level();

	mipi_dsi_mdp_busy_wait(mfd);
#ifdef MDP_UNDERFLOW_RESET_CTRL_CMD
	spin_lock_irqsave(&mixer_reset_lock, rflag);
#endif
	if (dsi_pipe->blt_addr == 0)
		mipi_dsi_cmd_mdp_start();

	mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);

	spin_lock_irqsave(&mdp_spin_lock, flag);

	mdp_enable_irq(MDP_OVERLAY0_TERM);
	mfd->dma->busy = TRUE;

	if (dsi_pipe->blt_addr)
		mfd->dma->dmap_busy = TRUE;

	/* start OVERLAY pipe */
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
	mdp4_stat.kickoff_ov0++;
#ifdef MDP_UNDERFLOW_RESET_CTRL_CMD
	spin_unlock_irqrestore(&mixer_reset_lock, rflag);
#endif
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
				struct mdp4_overlay_pipe *pipe)
{
	unsigned long flag;


	/* change mdp clk */
	mdp4_set_perf_level();

#ifndef MDP4_DSI_SW_TRIGGER
	mipi_dsi_mdp_busy_wait(mfd);
	if (dsi_pipe->blt_addr == 0)
		mipi_dsi_cmd_mdp_start();
#endif

	mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);

	spin_lock_irqsave(&mdp_spin_lock, flag);
	mdp_enable_irq(MDP_OVERLAY0_TERM);
	mfd->dma->busy = TRUE;
	if (dsi_pipe->blt_addr)
		mfd->dma->dmap_busy = TRUE;
	/* start OVERLAY pipe */
	wmb();
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
	wmb();

	mdp4_stat.kickoff_ov0++;
#ifdef MDP4_DSI_SW_TRIGGER
	if (dsi_pipe->blt_addr == 0) {
		/* trigger dsi cmd engine */
		mipi_dsi_cmd_mdp_sw_trigger(mfd);
	}
#endif
}
示例#17
0
void mdp4_overlay_dtv_wait_for_ov(struct msm_fb_data_type *mfd,
	struct mdp4_overlay_pipe *pipe)
{
	mdp4_overlay_dtv_wait4_ov_done(mfd, pipe);
	mdp4_set_perf_level();
}
示例#18
0
void mdp4_overlay_dsi_video_set_perf(struct msm_fb_data_type *mfd)
{
	mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
	/* change mdp clk while mdp is idle */
	mdp4_set_perf_level();
}
void mdp4_overlay_dtv_set_perf(struct msm_fb_data_type *mfd)
{
	/* change mdp clk while mdp is idle` */
	mdp4_set_perf_level();
}