int mdp_lcdc_off(struct platform_device *pdev) { int ret = 0; /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); MDP_OUTP(MDP_BASE + LCDC_BASE, 0); /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_histogram_ctrl(FALSE); ret = panel_next_off(pdev); /* delay to make sure the last frame finishes */ msleep(16); #ifdef LCDC_RGB_UNSTAGE /* dis-engage rgb0 from mixer0 */ if (lcdc_pipe) mdp4_mixer_stage_down(lcdc_pipe); #endif #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif return ret; }
static int lcdc_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; mfd = platform_get_drvdata(pdev); ret = panel_next_off(pdev); clk_disable(pixel_mdp_clk); clk_disable(pixel_lcdc_clk); #ifdef CONFIG_FB_MSM_LCDC_LEAD_WVGA_PANEL //ZTE_LCD_LHT_20100810_001 if(LcdPanleID!=72) { if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(0); } #endif if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config) ret = lcdc_pdata->lcdc_gpio_config(0); #ifndef CONFIG_MSM_BUS_SCALING if (mfd->ebi1_clk) clk_disable(mfd->ebi1_clk); #else mdp_bus_scale_update_request(0); #endif return ret; }
static int lcdc_on(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; unsigned long panel_pixclock_freq = 0; #ifndef CONFIG_MSM_BUS_SCALING unsigned long pm_qos_rate; #endif mfd = platform_get_drvdata(pdev); if (lcdc_pdata && lcdc_pdata->lcdc_get_clk) panel_pixclock_freq = lcdc_pdata->lcdc_get_clk(); if (!panel_pixclock_freq) panel_pixclock_freq = mfd->fbi->var.pixclock; #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #else if (panel_pixclock_freq > 65000000) /* pm_qos_rate should be in Khz */ pm_qos_rate = panel_pixclock_freq / 1000 ; else pm_qos_rate = 65000; if (mfd->ebi1_clk) { if (mdp_rev == MDP_REV_303) { if (clk_set_rate(mfd->ebi1_clk, 65000000)) pr_err("%s: ebi1_lcdc_clk set rate failed\n", __func__); } else { clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000); } clk_prepare_enable(mfd->ebi1_clk); } #endif mfd = platform_get_drvdata(pdev); mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); if (ret) { pr_err("%s: Can't set MDP LCDC pixel clock to rate %u\n", __func__, mfd->fbi->var.pixclock); goto out; } clk_prepare_enable(pixel_mdp_clk); clk_prepare_enable(pixel_lcdc_clk); if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(1); if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config) ret = lcdc_pdata->lcdc_gpio_config(1); ret = panel_next_on(pdev); out: return ret; }
static int lcdc_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; mfd = platform_get_drvdata(pdev); ret = panel_next_off(pdev); clk_disable(pixel_mdp_clk); clk_disable(pixel_lcdc_clk); if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(0); if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config) ret = lcdc_pdata->lcdc_gpio_config(0); #ifndef CONFIG_MSM_BUS_SCALING if (mdp_rev != MDP_REV_303) { if (mfd->ebi1_clk) clk_disable(mfd->ebi1_clk); } #else mdp_bus_scale_update_request(0); #endif return ret; }
static int lvds_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; mfd = platform_get_drvdata(pdev); ret = panel_next_off(pdev); if (lvds_clk) clk_disable_unprepare(lvds_clk); MDP_OUTP(MDP_BASE + 0xc3100, 0x0); MDP_OUTP(MDP_BASE + 0xc3000, 0x0); usleep(10); if (lvds_pdata && lvds_pdata->lcdc_power_save) lvds_pdata->lcdc_power_save(0); if (lvds_pdata && lvds_pdata->lcdc_gpio_config) ret = lvds_pdata->lcdc_gpio_config(0); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif return ret; }
static int mddi_off(struct platform_device *pdev) { struct msm_fb_data_type *mfd; boolean dma_pending, dma_update_flag; int ret, i; mfd = platform_get_drvdata(pdev); for (i = 0; i < 6; i++) { dma_update_flag = mfd->dma_update_flag; dma_pending = mfd->dma->busy; if (dma_update_flag && !dma_pending) break; msleep(5); } pmdh_clk_enable(); ret = panel_next_off(pdev); pmdh_clk_disable(); if (mddi_pdata && mddi_pdata->mddi_power_save) mddi_pdata->mddi_power_save(0); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #else if (mfd->ebi1_clk) clk_disable_unprepare(mfd->ebi1_clk); #endif pm_runtime_put(&pdev->dev); return ret; }
static int lcdc_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; mfd = platform_get_drvdata(pdev); ret = panel_next_off(pdev); clk_disable(pixel_mdp_clk); clk_disable(pixel_lcdc_clk); #ifdef CONFIG_FB_MSM_LCDC_OLED_WVGA if(LcdPanleID!=42) { if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(0); } #elif defined(CONFIG_FB_MSM_LCDC_SKATE_WVGA) #else if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(0); #endif /* if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config) ret = lcdc_pdata->lcdc_gpio_config(0);*/ #ifndef CONFIG_MSM_BUS_SCALING if (mfd->ebi1_clk) clk_disable(mfd->ebi1_clk); #else mdp_bus_scale_update_request(0); #endif return ret; }
static int lcdc_on(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; unsigned long panel_pixclock_freq = 0; #ifndef CONFIG_MSM_BUS_SCALING unsigned long pm_qos_rate; #endif mfd = platform_get_drvdata(pdev); if (lcdc_pdata && lcdc_pdata->lcdc_get_clk) panel_pixclock_freq = lcdc_pdata->lcdc_get_clk(); if (!panel_pixclock_freq) panel_pixclock_freq = mfd->fbi->var.pixclock; #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #else #ifdef CONFIG_MSM_NPA_SYSTEM_BUS pm_qos_rate = MSM_AXI_FLOW_MDP_LCDC_WVGA_2BPP; #else if (panel_pixclock_freq > 65000000) /* pm_qos_rate should be in Khz */ pm_qos_rate = panel_pixclock_freq / 1000 ; else pm_qos_rate = 65000; #endif if (mfd->ebi1_clk) { clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000); clk_enable(mfd->ebi1_clk); } #endif mfd = platform_get_drvdata(pdev); mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); if (ret) { pr_err("%s: Can't set MDP LCDC pixel clock to rate %u\n", __func__, mfd->fbi->var.pixclock); goto out; } clk_enable(pixel_mdp_clk); clk_enable(pixel_lcdc_clk); pr_info("@LCDINIT@:DOTCLK clock enabled\n"); if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(1); if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config) ret = lcdc_pdata->lcdc_gpio_config(1); ret = panel_next_on(pdev); out: return ret; }
int mdp_lcdc_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; { // taeyol unsigned long flag; spin_lock_irqsave(&mdp_spin_lock, flag); mdp4_lcdc_on_state = FALSE; spin_unlock_irqrestore(&mdp_spin_lock, flag); } mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); mutex_lock(&mfd->dma->ov_mutex); /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); MDP_OUTP(MDP_BASE + LCDC_BASE, 0); lcdc_enabled = 0; /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_histogram_ctrl_all(FALSE); ret = panel_next_off(pdev); mutex_unlock(&mfd->dma->ov_mutex); /* delay to make sure the last frame finishes */ msleep(16); /* dis-engage rgb0 from mixer0 */ if (lcdc_pipe) { mdp4_mixer_stage_down(lcdc_pipe); mdp4_iommu_unmap(lcdc_pipe); } #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif complete_all(&lcdc_comp); // taeyol return ret; }
int set_lcdc_clk(struct fb_info *fbi) { int ret = 0; struct msm_fb_data_type *mfd; unsigned long panel_pixclock_freq = 0; #ifndef CONFIG_MSM_BUS_SCALING unsigned long pm_qos_rate; #endif mfd = (struct msm_fb_data_type *)fbi->par; #ifndef CONFIG_MSM_BUS_SCALING pixel_ebi_clk = mfd->ebi1_clk; #endif if (lcdc_pdata && lcdc_pdata->lcdc_get_clk) panel_pixclock_freq = lcdc_pdata->lcdc_get_clk(); if (!panel_pixclock_freq) panel_pixclock_freq = mfd->fbi->var.pixclock; #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #else #ifdef CONFIG_MSM_NPA_SYSTEM_BUS pm_qos_rate = MSM_AXI_FLOW_MDP_LCDC_WVGA_2BPP; #else if (panel_pixclock_freq > 65000000) /* pm_qos_rate should be in Khz */ pm_qos_rate = panel_pixclock_freq / 1000 ; else pm_qos_rate = 65000; #endif g_ebi1_clk_rate_old = clk_get_rate(mfd->ebi1_clk); g_ebi1_clk_rate = pm_qos_rate * 1000; #endif mfd = (struct msm_fb_data_type *)fbi->par; g_pixel_mdp_clk_rate_old = clk_get_rate(pixel_mdp_clk); mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); g_pixel_mdp_clk_rate = mfd->fbi->var.pixclock; g_mdp_lcdc_clk_set_flag = 1; // pr_err("%s: set pclk %u 1111111111\n",__func__, g_pixel_mdp_clk_rate); return ret; }
int mdp_lcdc_off(struct platform_device *pdev) { int ret = 0; uint32 data; #ifdef CONFIG_FB_MSM_LCDC_LEAD_WVGA_PANEL //ZTE_LCD_LHT_20100810_001 if(LcdPanleID==72) lcdc_lead_sleep(); #endif #ifdef CONFIG_FB_MSM_LCDC_WVGA_ARTHUR if(LcdPanleID==60) lcdc_lead_sleep(); if(LcdPanleID==61) lcdc_truly_sleep(); #endif /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); MDP_OUTP(MDP_BASE + LCDC_BASE, 0); /* MDP cmd block disable */ data = inpdw(MDP_BASE + 0x10100); data = data&0xffffff00; outpdw(MDP_BASE + 0x10100, data); mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_histogram_ctrl(FALSE); ret = panel_next_off(pdev); /* delay to make sure the last frame finishes */ msleep(16); #ifdef LCDC_RGB_UNSTAGE /* dis-engage rgb0 from mixer0 */ if (lcdc_pipe) mdp4_mixer_stage_down(lcdc_pipe); #endif #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif return ret; }
static int lvds_on(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; unsigned long panel_pixclock_freq = 0; mfd = platform_get_drvdata(pdev); if (lvds_pdata && lvds_pdata->lcdc_get_clk) panel_pixclock_freq = lvds_pdata->lcdc_get_clk(); if (!panel_pixclock_freq) panel_pixclock_freq = mfd->fbi->var.pixclock; #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #endif mfd = platform_get_drvdata(pdev); if (lvds_clk) { mfd->fbi->var.pixclock = clk_round_rate(lvds_clk, mfd->fbi->var.pixclock); ret = clk_set_rate(lvds_clk, mfd->fbi->var.pixclock); if (ret) { pr_err("%s: Can't set lvds clock to rate %u\n", __func__, mfd->fbi->var.pixclock); goto out; } clk_prepare_enable(lvds_clk); } if (lvds_pdata && lvds_pdata->lcdc_power_save) lvds_pdata->lcdc_power_save(1); if (lvds_pdata && lvds_pdata->lcdc_gpio_config) ret = lvds_pdata->lcdc_gpio_config(1); lvds_init(mfd); ret = panel_next_on(pdev); out: return ret; }
int mdp_lcdc_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); mutex_lock(&mfd->dma->ov_mutex); /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); mdp4_mixer_pipe_cleanup(lcdc_pipe->mixer_num); MDP_OUTP(MDP_BASE + LCDC_BASE, 0); lcdc_enabled = 0; /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); mdp_histogram_ctrl_all(FALSE); ret = panel_next_off(pdev); mutex_unlock(&mfd->dma->ov_mutex); /* delay to make sure the last frame finishes */ msleep(20); /* dis-engage rgb0 from mixer0 */ if (lcdc_pipe) { mdp4_mixer_stage_down(lcdc_pipe); mdp4_iommu_unmap(lcdc_pipe); } #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif mdp4_iommu_detach(); return ret; }
static int mipi_dsi_on(struct platform_device *pdev) { int ret = 0; u32 clk_rate; struct msm_fb_data_type *mfd; struct fb_info *fbi; struct fb_var_screeninfo *var; struct msm_panel_info *pinfo; struct mipi_panel_info *mipi; u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height; u32 ystride, bpp, data; u32 dummy_xres, dummy_yres; int target_type = 0; mfd = platform_get_drvdata(pdev); fbi = mfd->fbi; var = &fbi->var; pinfo = &mfd->panel_info; if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(1); #if defined(CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11) /* * Fix for floating state of VDD line in toshiba chip * */ if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_client_power_save) mipi_dsi_pdata->dsi_client_power_save(1); #endif /* CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11 */ cont_splash_clk_ctrl(); local_bh_disable(); mipi_dsi_ahb_ctrl(1); local_bh_enable(); clk_rate = mfd->fbi->var.pixclock; clk_rate = min(clk_rate, mfd->panel_info.clk_max); MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1); MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0); hbp = var->left_margin; hfp = var->right_margin; vbp = var->upper_margin; vfp = var->lower_margin; hspw = var->hsync_len; vspw = var->vsync_len; width = mfd->panel_info.xres; height = mfd->panel_info.yres; mipi_dsi_phy_ctrl(1); if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata) target_type = mipi_dsi_pdata->target_type; mipi_dsi_phy_init(0, &(mfd->panel_info), target_type); local_bh_disable(); mipi_dsi_clk_enable(); local_bh_enable(); mipi = &mfd->panel_info.mipi; if (mfd->panel_info.type == MIPI_VIDEO_PANEL) { dummy_xres = mfd->panel_info.mipi.xres_pad; dummy_yres = mfd->panel_info.mipi.yres_pad; if (mdp_rev >= MDP_REV_41) { MIPI_OUTP(MIPI_DSI_BASE + 0x20, ((hspw + hbp + width + dummy_xres) << 16 | (hspw + hbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x24, ((vspw + vbp + height + dummy_yres) << 16 | (vspw + vbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x28, (vspw + vbp + height + dummy_yres + vfp - 1) << 16 | (hspw + hbp + width + dummy_xres + hfp - 1)); } else { /* DSI_LAN_SWAP_CTRL */ MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap); MIPI_OUTP(MIPI_DSI_BASE + 0x20, ((hbp + width + dummy_xres) << 16 | (hbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x24, ((vbp + height + dummy_yres) << 16 | (vbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x28, (vbp + height + dummy_yres + vfp) << 16 | (hbp + width + dummy_xres + hfp)); } MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16)); MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0); MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16)); } else { /* command mode */ if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888) bpp = 3; else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666) bpp = 3; else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565) bpp = 2; else bpp = 3; /* Default format set to RGB888 */ ystride = width * bpp + 1; /* DSI_COMMAND_MODE_MDP_STREAM_CTRL */ data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE; MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data); MIPI_OUTP(MIPI_DSI_BASE + 0x54, data); /* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */ data = height << 16 | width; MIPI_OUTP(MIPI_DSI_BASE + 0x60, data); MIPI_OUTP(MIPI_DSI_BASE + 0x58, data); } mipi_dsi_host_init(mipi); #if defined(CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11) /* * For TC358764 D2L IC, one of the requirement for power on * is to maintain an LP11 state in data and clock lanes during * power enabling and reset assertion. This change is to * achieve that. * */ if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_client_power_save) { u32 tmp_reg0c, tmp_rega8; mipi_dsi_pdata->dsi_client_reset(); udelay(200); /* backup register values */ tmp_reg0c = MIPI_INP(MIPI_DSI_BASE + 0x000c); tmp_rega8 = MIPI_INP(MIPI_DSI_BASE + 0xA8); /* Clear HS mode assertion and related flags */ MIPI_OUTP(MIPI_DSI_BASE + 0x0c, 0x8000); MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x0); wmb(); mdelay(5); /* restore previous values */ MIPI_OUTP(MIPI_DSI_BASE + 0x0c, tmp_reg0c); MIPI_OUTP(MIPI_DSI_BASE + 0xa8, tmp_rega8); wmb(); } #endif /* CONFIG_FB_MSM_MIPI_PANEL_POWERON_LP11 */ if (mipi->force_clk_lane_hs) { u32 tmp; tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8); tmp |= (1<<28); MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp); wmb(); } if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); ret = panel_next_on(pdev); mipi_dsi_op_mode_config(mipi->mode); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (mdp_rev >= MDP_REV_41) { if (gpio_request(vsync_gpio, "MDP_VSYNC") == 0) gpio_direction_input( vsync_gpio); else pr_err("%s: unable to request gpio=%d\n", __func__, vsync_gpio); } else if (mdp_rev == MDP_REV_303) { if (!tlmm_settings && gpio_request( vsync_gpio, "MDP_VSYNC") == 0) { ret = gpio_tlmm_config( GPIO_CFG( vsync_gpio, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), GPIO_CFG_ENABLE); if (ret) { pr_err("%s: unable to config tlmm = %d\n", __func__, vsync_gpio); } tlmm_settings = TRUE; gpio_direction_input( vsync_gpio); } else { if (!tlmm_settings) { pr_err("%s: unable to request gpio=%d\n", __func__, vsync_gpio); } } } } mipi_dsi_set_tear_on(mfd); } } #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #endif mdp4_overlay_dsi_state_set(ST_DSI_RESUME); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif #if defined(CONFIG_FB_MSM_MIPI_S6E8AA0_HD720_PANEL) || \ defined(CONFIG_FB_MSM_MIPI_S6E8AA0_WXGA_Q1_PANEL) MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x00000000); // for LCD-on when wakeup #endif spin_lock_bh(&dsi_clk_lock); mipi_dsi_clk_disable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); mipi_dsi_ahb_ctrl(0); spin_unlock_bh(&dsi_clk_lock); mipi_dsi_unprepare_clocks(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; pr_debug("%s+:\n", __func__); mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; printk(KERN_INFO"%s is started.. \n", __func__); if (mdp_rev >= MDP_REV_41 && mfd->panel_info.type == MIPI_CMD_PANEL) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); if (mfd->panel_info.type == MIPI_CMD_PANEL) { mipi_dsi_prepare_clocks(); mipi_dsi_ahb_ctrl(1); mipi_dsi_clk_enable(); /* make sure dsi_cmd_mdp is idle */ mipi_dsi_cmd_mdp_busy(); } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ #if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) \ || defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) \ || defined(CONFIG_FB_MSM_MIPI_DSI_LGIT_FHD) //for power sequence of lgit panel #else mipi_dsi_op_mode_config(DSI_CMD_MODE); #endif if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } #if defined(CONFIG_FB_MSM_MIPI_LGIT_VIDEO_WXGA_PT) \ || defined(CONFIG_FB_MSM_MIPI_HITACHI_VIDEO_HD_PT) \ || defined(CONFIG_FB_MSM_MIPI_DSI_LGIT_FHD) //for power sequence of lgit panel. #else ret = panel_next_off(pdev); #endif #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif mipi_dsi_clk_disable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); mipi_dsi_ahb_ctrl(0); mipi_dsi_unprepare_clocks(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41 && mfd->panel_info.type == MIPI_CMD_PANEL) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("End of %s ....:\n", __func__); printk(KERN_INFO"%s is ended.. \n", __func__); return ret; }
static int lcdc_on(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; unsigned long panel_pixclock_freq = 0; #ifndef CONFIG_MSM_BUS_SCALING unsigned long pm_qos_rate; #endif #if !defined (CONFIG_MACH_CHIEF) if(lcd_clk_enable) return; #endif mfd = platform_get_drvdata(pdev); #if defined CONFIG_MACH_CHIEF || defined CONFIG_MACH_VITAL2 //chief.sony.lcd lcd power up sequence changed // vdd, vcc power on before dotclk (sony & smd) if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(1); #endif if (lcdc_pdata && lcdc_pdata->lcdc_get_clk) panel_pixclock_freq = lcdc_pdata->lcdc_get_clk(); if (!panel_pixclock_freq) panel_pixclock_freq = mfd->fbi->var.pixclock; #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #else #ifdef CONFIG_MSM_NPA_SYSTEM_BUS pm_qos_rate = MSM_AXI_FLOW_MDP_LCDC_WVGA_2BPP; #else if (panel_pixclock_freq > 65000000) /* pm_qos_rate should be in Khz */ pm_qos_rate = panel_pixclock_freq / 1000 ; else pm_qos_rate = 65000; #endif if (mfd->ebi1_clk) { clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000); clk_enable(mfd->ebi1_clk); } #endif mfd = platform_get_drvdata(pdev); mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock); if (ret) { pr_err("%s: Can't set MDP LCDC pixel clock to rate %u\n", __func__, mfd->fbi->var.pixclock); goto out; } clk_enable(pixel_mdp_clk); clk_enable(pixel_lcdc_clk); #if defined CONFIG_MACH_VITAL2 printk("%s %15s:%4d\n",__func__,current->comm,task_pid_nr(current)); if(strcmp(current->comm,"suspend") && strcmp(current->comm,"swapper")){ exception_cnt++; } #endif pr_info("@LCDINIT@:DOTCLK clock enabled\n"); #if !defined (CONFIG_MACH_CHIEF) lcd_clk_enable = TRUE; #endif #if defined CONFIG_MACH_CHIEF || defined CONFIG_MACH_VITAL2 //chief.sony.lcd lcd power up sequence changed //wait for clock to stabilize msleep(20); #endif #if !defined CONFIG_MACH_CHIEF && !defined CONFIG_MACH_VITAL2 //chief.sony.lcd lcd power up sequence changed if (lcdc_pdata && lcdc_pdata->lcdc_power_save) lcdc_pdata->lcdc_power_save(1); #endif if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config) ret = lcdc_pdata->lcdc_gpio_config(1); #ifdef CONFIG_MACH_VITAL2 mdp4_overlay_block_on(); #endif // start disp on sequence ret = panel_next_on(pdev); out: return ret; }
/*LGE_CHANGE_E LCD Reset After Data Pulled Down*/ static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ //LGE_CHANGE_S [Kiran] Change LCD sleep sequence /*LCD Reset After data pulled Down*/ #if 0 if(lglogo_firstboot) { mipi_dsi_op_mode_config(DSI_CMD_MODE); } #endif /*LGE_CHANGE_E LCD Reset After Data Pulled Down*/ //LGE_CHANGE_E [Kiran] Change LCD sleep sequence if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif /*In case of ESD no delays required in power off*/ //LGE_CHANGE_S [Kiran] Change LCD sleep sequence #ifdef CONFIG_LGE_LCD_ESD_DETECTION if (true == is_esd_occured) { printk("ESD.Paneloff ASAP\n"); } else #endif msleep(300); //LGE_CHANGE_E [Kiran] Change LCD sleep sequence #ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO if(lglogo_firstboot) { printk(KERN_INFO "[DISPLAY]::%s\n",__func__); local_bh_disable(); lglogo_mipi_dsi_clk_disable(); local_bh_enable(); } else #endif { local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); } /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); #ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO if(!lglogo_firstboot) #endif { local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); } //LGE_CHANGE_S [Kiran] Change LCD sleep sequence #if 1 /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0); /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); /*Turning off DMA_P block*/ mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); #endif //LGE_CHANGE_E [Kiran] Change LCD sleep sequence /*LCD Reset After data pulled Down*/ mipi_ldp_lcd_panel_poweroff(); /*LGE_CHANGE_E LCD Reset After Data Pulled Down*/ if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); #ifdef CONFIG_FB_MSM_MIPI_DSI_LG4573B_BOOT_LOGO lglogo_firstboot = FALSE; #endif return ret; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else htc_mdp_sem_down(current, &mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); mipi_dsi_clk_cfg(1); mipi_dsi_cmd_mdp_busy(); mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } if (panel_type != PANEL_ID_PROTOU_LG && panel_type != PANEL_ID_PROTODCG_LG) ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif spin_lock_bh(&dsi_clk_lock); mipi_dsi_clk_disable(); MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); mipi_dsi_ahb_ctrl(0); spin_unlock_bh(&dsi_clk_lock); mipi_dsi_unprepare_clocks(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else htc_mdp_sem_up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
static int mipi_dsi_on(struct platform_device *pdev) { int ret = 0; u32 clk_rate; struct msm_fb_data_type *mfd; struct fb_info *fbi; struct fb_var_screeninfo *var; struct msm_panel_info *pinfo; struct mipi_panel_info *mipi; u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height; u32 ystride, bpp, data; u32 dummy_xres, dummy_yres; int target_type = 0; mfd = platform_get_drvdata(pdev); fbi = mfd->fbi; var = &fbi->var; pinfo = &mfd->panel_info; if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(1); clk_rate = mfd->fbi->var.pixclock; clk_rate = min(clk_rate, mfd->panel_info.clk_max); local_bh_disable(); mipi_dsi_clk_enable(); local_bh_enable(); #ifndef CONFIG_FB_MSM_MDP303 mdp4_overlay_dsi_state_set(ST_DSI_RESUME); #endif MIPI_OUTP(MIPI_DSI_BASE + 0x114, 1); MIPI_OUTP(MIPI_DSI_BASE + 0x114, 0); hbp = var->left_margin; hfp = var->right_margin; vbp = var->upper_margin; vfp = var->lower_margin; hspw = var->hsync_len; vspw = var->vsync_len; width = mfd->panel_info.xres; height = mfd->panel_info.yres; mipi_dsi_phy_ctrl(1); if (mdp_rev == MDP_REV_42 && mipi_dsi_pdata) target_type = mipi_dsi_pdata->target_type; mipi_dsi_phy_init(0, &(mfd->panel_info), target_type); mipi = &mfd->panel_info.mipi; if (mfd->panel_info.type == MIPI_VIDEO_PANEL) { dummy_xres = mfd->panel_info.mipi.xres_pad; dummy_yres = mfd->panel_info.mipi.yres_pad; if (mdp_rev >= MDP_REV_41) { MIPI_OUTP(MIPI_DSI_BASE + 0x20, ((hspw + hbp + width + dummy_xres) << 16 | (hspw + hbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x24, ((vspw + vbp + height + dummy_yres) << 16 | (vspw + vbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x28, (vspw + vbp + height + dummy_yres + vfp - 1) << 16 | (hspw + hbp + width + dummy_xres + hfp - 1)); } else { /* DSI_LAN_SWAP_CTRL */ MIPI_OUTP(MIPI_DSI_BASE + 0x00ac, mipi->dlane_swap); MIPI_OUTP(MIPI_DSI_BASE + 0x20, ((hbp + width + dummy_xres) << 16 | (hbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x24, ((vbp + height + dummy_yres) << 16 | (vbp))); MIPI_OUTP(MIPI_DSI_BASE + 0x28, (vbp + height + dummy_yres + vfp) << 16 | (hbp + width + dummy_xres + hfp)); } MIPI_OUTP(MIPI_DSI_BASE + 0x2c, (hspw << 16)); MIPI_OUTP(MIPI_DSI_BASE + 0x30, 0); MIPI_OUTP(MIPI_DSI_BASE + 0x34, (vspw << 16)); } else { /* command mode */ if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888) bpp = 3; else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666) bpp = 3; else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565) bpp = 2; else bpp = 3; /* Default format set to RGB888 */ ystride = width * bpp + 1; /* DSI_COMMAND_MODE_MDP_STREAM_CTRL */ data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE; MIPI_OUTP(MIPI_DSI_BASE + 0x5c, data); MIPI_OUTP(MIPI_DSI_BASE + 0x54, data); /* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */ data = height << 16 | width; MIPI_OUTP(MIPI_DSI_BASE + 0x60, data); MIPI_OUTP(MIPI_DSI_BASE + 0x58, data); } mipi_dsi_host_init(mipi); mipi_dsi_cmd_bta_sw_trigger(); /* clean up ack_err_status */ ret = panel_next_on(pdev); mipi_dsi_op_mode_config(mipi->mode); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) { if (gpio_request(vsync_gpio, "MDP_VSYNC") == 0) gpio_direction_input(vsync_gpio); else pr_err("%s: unable to request gpio=%d\n", __func__, vsync_gpio); } mipi_dsi_set_tear_on(mfd); } } #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #endif return ret; }
/* LGE_UPDATE_E [email protected] 20110717 hidden_reset_porting from Victor. */ int mdp_lcdc_on(struct platform_device *pdev) { int lcdc_width; int lcdc_height; int lcdc_bpp; int lcdc_border_clr; int lcdc_underflow_clr; int lcdc_hsync_skew; int hsync_period; int hsync_ctrl; int vsync_period; int display_hctl; int display_v_start; int display_v_end; int active_hctl; int active_h_start; int active_h_end; int active_v_start; int active_v_end; int ctrl_polarity; int h_back_porch; int h_front_porch; int v_back_porch; int v_front_porch; int hsync_pulse_width; int vsync_pulse_width; int hsync_polarity; int vsync_polarity; int data_en_polarity; int hsync_start_x; int hsync_end_x; uint8 *buf; unsigned int buf_offset; int bpp, ptype; struct fb_info *fbi; struct fb_var_screeninfo *var; struct msm_fb_data_type *mfd; struct mdp4_overlay_pipe *pipe; int ret; mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); if (!mfd) return -ENODEV; if (mfd->key != MFD_KEY) return -EINVAL; mdp4_overlay_ctrl_db_reset(); fbi = mfd->fbi; var = &fbi->var; /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); if (is_mdp4_hw_reset()) { mdp4_hw_init(); outpdw(MDP_BASE + 0x0038, mdp4_display_intf); } bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf_offset = calc_fb_offset(mfd, fbi, bpp); if (lcdc_pipe == NULL) { ptype = mdp4_overlay_format2type(mfd->fb_imgType); if (ptype < 0) printk(KERN_INFO "%s: format2type failed\n", __func__); pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0); if (pipe == NULL) printk(KERN_INFO "%s: pipe_alloc failed\n", __func__); pipe->pipe_used++; pipe->mixer_stage = MDP4_MIXER_STAGE_BASE; pipe->mixer_num = MDP4_MIXER0; pipe->src_format = mfd->fb_imgType; mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_LCDC); ret = mdp4_overlay_format2pipe(pipe); if (ret < 0) printk(KERN_INFO "%s: format2pipe failed\n", __func__); lcdc_pipe = pipe; /* keep it */ init_completion(&lcdc_comp); mdp4_init_writeback_buf(mfd, MDP4_MIXER0); pipe->blt_addr = 0; } else { pipe = lcdc_pipe; } pipe->src_height = fbi->var.yres; pipe->src_width = fbi->var.xres; pipe->src_h = fbi->var.yres; pipe->src_w = fbi->var.xres; pipe->src_y = 0; pipe->src_x = 0; if (mfd->map_buffer) { pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \ buf_offset; pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd-> map_buffer->iova[0], pipe->srcp0_addr); } else { pipe->srcp0_addr = (uint32)(buf + buf_offset); } pipe->srcp0_ystride = fbi->fix.line_length; pipe->bpp = bpp; mdp4_overlay_dmap_xy(pipe); mdp4_overlay_dmap_cfg(mfd, 1); mdp4_overlay_rgb_setup(pipe); mdp4_mixer_stage_up(pipe); mdp4_overlayproc_cfg(pipe); /* * LCDC timing setting */ h_back_porch = var->left_margin; h_front_porch = var->right_margin; v_back_porch = var->upper_margin; v_front_porch = var->lower_margin; hsync_pulse_width = var->hsync_len; vsync_pulse_width = var->vsync_len; lcdc_border_clr = mfd->panel_info.lcdc.border_clr; lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr; lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew; lcdc_width = var->xres; lcdc_height = var->yres; lcdc_bpp = mfd->panel_info.bpp; hsync_period = hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch; hsync_ctrl = (hsync_period << 16) | hsync_pulse_width; hsync_start_x = hsync_pulse_width + h_back_porch; hsync_end_x = hsync_period - h_front_porch - 1; display_hctl = (hsync_end_x << 16) | hsync_start_x; vsync_period = (vsync_pulse_width + v_back_porch + lcdc_height + v_front_porch) * hsync_period; display_v_start = (vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew; display_v_end = vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1; if (lcdc_width != var->xres) { active_h_start = hsync_start_x + first_pixel_start_x; active_h_end = active_h_start + var->xres - 1; active_hctl = ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start; } else { active_hctl = 0; } if (lcdc_height != var->yres) { active_v_start = display_v_start + first_pixel_start_y * hsync_period; active_v_end = active_v_start + (var->yres) * hsync_period - 1; active_v_start |= ACTIVE_START_Y_EN; } else { active_v_start = 0; active_v_end = 0; } #ifdef CONFIG_FB_MSM_MDP40 hsync_polarity = 1; vsync_polarity = 1; lcdc_underflow_clr |= 0x80000000; /* enable recovery */ #else hsync_polarity = 0; vsync_polarity = 0; #endif data_en_polarity = 0; ctrl_polarity = (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x4, hsync_ctrl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x8, vsync_period); MDP_OUTP(MDP_BASE + LCDC_BASE + 0xc, vsync_pulse_width * hsync_period); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x10, display_hctl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x14, display_v_start); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x18, display_v_end); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x28, lcdc_border_clr); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x2c, lcdc_underflow_clr); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x30, lcdc_hsync_skew); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x38, ctrl_polarity); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x1c, active_hctl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x20, active_v_start); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x24, active_v_end); mdp4_overlay_reg_flush(pipe, 1); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #endif mdp_histogram_ctrl_all(TRUE); /* LGE_UPDATE_S [email protected] QCT404032I patch */ #if 0 mdp_intr_mask &= ~(INTR_OVERLAY0_DONE | INTR_DMA_P_DONE); mdp_intr_mask |= INTR_PRIMARY_VSYNC; /* listen on vsycn only */ outp32(MDP_INTR_ENABLE, mdp_intr_mask); mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */ #endif /* LGE_UPDATE_E [email protected] QCT404032I patch */ #ifdef CONFIG_FB_MSM_LCDC_LGDISPLAY_WVGA_OLED /* LGE_CHANGE */ /* enable LCDC block */ MDP_OUTP(MDP_BASE + LCDC_BASE, 1); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE); msleep(16); ret = panel_next_on(pdev); #else ret = panel_next_on(pdev); #endif /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); if( ret >= 0 ) { // taeyol unsigned long flag; spin_lock_irqsave(&mdp_spin_lock, flag); mdp4_lcdc_on_state = TRUE; spin_unlock_irqrestore(&mdp_spin_lock, flag); } return ret; }
int mdp_lcdc_on(struct platform_device *pdev) { int lcdc_width; int lcdc_height; int lcdc_bpp; int lcdc_border_clr; int lcdc_underflow_clr; int lcdc_hsync_skew; int hsync_period; int hsync_ctrl; int vsync_period; int display_hctl; int display_v_start; int display_v_end; int active_hctl; int active_h_start; int active_h_end; int active_v_start; int active_v_end; int ctrl_polarity; int h_back_porch; int h_front_porch; int v_back_porch; int v_front_porch; int hsync_pulse_width; int vsync_pulse_width; int hsync_polarity; int vsync_polarity; int data_en_polarity; int hsync_start_x; int hsync_end_x; uint8 *buf; unsigned int buf_offset; int bpp, ptype; struct fb_info *fbi; struct fb_var_screeninfo *var; struct msm_fb_data_type *mfd; struct mdp4_overlay_pipe *pipe; int ret; mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); if (!mfd) return -ENODEV; if (mfd->key != MFD_KEY) return -EINVAL; mdp4_overlay_ctrl_db_reset(); fbi = mfd->fbi; var = &fbi->var; /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); if (is_mdp4_hw_reset()) { mdp4_hw_init(); outpdw(MDP_BASE + 0x0038, mdp4_display_intf); } bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf_offset = calc_fb_offset(mfd, fbi, bpp); if (lcdc_pipe == NULL) { ptype = mdp4_overlay_format2type(mfd->fb_imgType); if (ptype < 0) printk(KERN_INFO "%s: format2type failed\n", __func__); pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0); if (pipe == NULL) printk(KERN_INFO "%s: pipe_alloc failed\n", __func__); pipe->pipe_used++; pipe->mixer_stage = MDP4_MIXER_STAGE_BASE; pipe->mixer_num = MDP4_MIXER0; pipe->src_format = mfd->fb_imgType; mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_LCDC); ret = mdp4_overlay_format2pipe(pipe); if (ret < 0) printk(KERN_INFO "%s: format2pipe failed\n", __func__); lcdc_pipe = pipe; /* keep it */ init_completion(&lcdc_comp); mdp4_init_writeback_buf(mfd, MDP4_MIXER0); pipe->blt_addr = 0; } else { pipe = lcdc_pipe; } pipe->src_height = fbi->var.yres; pipe->src_width = fbi->var.xres; pipe->src_h = fbi->var.yres; pipe->src_w = fbi->var.xres; pipe->src_y = 0; pipe->src_x = 0; if (mfd->map_buffer) { pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \ buf_offset; pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd-> map_buffer->iova[0], pipe->srcp0_addr); } else { pipe->srcp0_addr = (uint32)(buf + buf_offset); } pipe->srcp0_ystride = fbi->fix.line_length; pipe->bpp = bpp; mdp4_overlay_dmap_xy(pipe); mdp4_overlay_dmap_cfg(mfd, 1); mdp4_overlay_rgb_setup(pipe); mdp4_mixer_stage_up(pipe); mdp4_overlayproc_cfg(pipe); /* * LCDC timing setting */ h_back_porch = var->left_margin; h_front_porch = var->right_margin; v_back_porch = var->upper_margin; v_front_porch = var->lower_margin; hsync_pulse_width = var->hsync_len; vsync_pulse_width = var->vsync_len; lcdc_border_clr = mfd->panel_info.lcdc.border_clr; lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr; lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew; lcdc_width = var->xres; lcdc_height = var->yres; lcdc_bpp = mfd->panel_info.bpp; hsync_period = hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch; hsync_ctrl = (hsync_period << 16) | hsync_pulse_width; hsync_start_x = hsync_pulse_width + h_back_porch; hsync_end_x = hsync_period - h_front_porch - 1; display_hctl = (hsync_end_x << 16) | hsync_start_x; vsync_period = (vsync_pulse_width + v_back_porch + lcdc_height + v_front_porch) * hsync_period; display_v_start = (vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew; display_v_end = vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1; if (lcdc_width != var->xres) { active_h_start = hsync_start_x + first_pixel_start_x; active_h_end = active_h_start + var->xres - 1; active_hctl = ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start; } else { active_hctl = 0; } if (lcdc_height != var->yres) { active_v_start = display_v_start + first_pixel_start_y * hsync_period; active_v_end = active_v_start + (var->yres) * hsync_period - 1; active_v_start |= ACTIVE_START_Y_EN; } else { active_v_start = 0; active_v_end = 0; } #if defined(CONFIG_SAMSUNG_LCDC_AUTO_DETECT) hsync_polarity = mfd->check_polarity("GET", 2); vsync_polarity = mfd->check_polarity("GET", 1); lcdc_underflow_clr |= 0x80000000; /* enable recovery */ data_en_polarity = mfd->check_polarity("GET", 0); #else /*If the model need to use both(active low and high)*/ hsync_polarity = 0; vsync_polarity = 0; lcdc_underflow_clr |= 0x80000000; /* enable recovery */ data_en_polarity = 0; #endif ctrl_polarity = (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x4, hsync_ctrl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x8, vsync_period); MDP_OUTP(MDP_BASE + LCDC_BASE + 0xc, vsync_pulse_width * hsync_period); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x10, display_hctl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x14, display_v_start); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x18, display_v_end); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x28, lcdc_border_clr); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x2c, lcdc_underflow_clr); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x30, lcdc_hsync_skew); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x38, ctrl_polarity); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x1c, active_hctl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x20, active_v_start); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x24, active_v_end); mdp4_overlay_reg_flush(pipe, 1); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #endif mdp_histogram_ctrl_all(TRUE); #ifdef CONFIG_SAMSUNG_LCDC_DISPLAY /* * LCDC Block must be enabled before the time of turn on lcd * because of the signal timing. */ mdp4_overlay_lcdc_start(); #endif ret = panel_next_on(pdev); /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); return ret; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; PR_DISP_DEBUG(" %s\n", __func__); mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else htc_mdp_sem_down(current, &mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio > 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else htc_mdp_sem_up(&mfd->dma->mutex); return ret; }
static int mddi_on(struct platform_device *pdev) { int ret = 0; u32 clk_rate; struct msm_fb_data_type *mfd; #ifdef ENABLE_FWD_LINK_SKEW_CALIBRATION mddi_host_type host_idx = MDDI_HOST_PRIM; u32 stat_reg; #endif mfd = platform_get_drvdata(pdev); pm_runtime_get(&pdev->dev); if (mddi_pdata && mddi_pdata->mddi_power_save) mddi_pdata->mddi_power_save(1); pmdh_clk_enable(); #ifdef ENABLE_FWD_LINK_SKEW_CALIBRATION if (mddi_client_type < 2) { /* For skew calibration, clock should be less than 50MHz */ clk_rate = clk_round_rate(mddi_clk, 49000000); if (!clk_set_rate(mddi_clk, clk_rate)) { stat_reg = mddi_host_reg_in(STAT); printk(KERN_DEBUG "\n stat_reg = 0x%x", stat_reg); mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE); if (stat_reg & (0x1 << 4)) mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE); mddi_host_reg_out(CMD, MDDI_CMD_SEND_RTD); mddi_send_fw_link_skew_cal(host_idx); mddi_host_reg_out(CMD, MDDI_CMD_SEND_RTD); mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1); } else { printk(KERN_ERR "%s: clk_set_rate failed\n", __func__); } } #endif clk_rate = mfd->fbi->var.pixclock; clk_rate = min(clk_rate, mfd->panel_info.clk_max); if (mddi_pdata && mddi_pdata->mddi_sel_clk && mddi_pdata->mddi_sel_clk(&clk_rate)) printk(KERN_ERR "%s: can't select mddi io clk targate rate = %d\n", __func__, clk_rate); clk_rate = clk_round_rate(mddi_clk, clk_rate); if (clk_set_rate(mddi_clk, clk_rate) < 0) printk(KERN_ERR "%s: clk_set_rate failed\n", __func__); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #else if (mfd->ebi1_clk) clk_prepare_enable(mfd->ebi1_clk); #endif ret = panel_next_on(pdev); return ret; }
int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } else { /* video mode, wait until fifo cleaned */ mipi_dsi_controller_cfg(0); } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif #if defined(CONFIG_FB_MSM_MIPI_S6E8AA0_HD720_PANEL) || \ defined(CONFIG_FB_MSM_MIPI_S6E8AA0_WXGA_Q1_PANEL) MIPI_OUTP(MIPI_DSI_BASE + 0xA8, 0x00000000); // for LCD-on when wakeup #endif local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
static void mipi_dsi_shutdown(struct platform_device *pdev) { if(bmipi_off == 0) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; pr_debug("Start of %s....:\n", __func__); mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); if (mfd->panel_info.type == MIPI_CMD_PANEL) { mipi_dsi_prepare_clocks(); mipi_dsi_ahb_ctrl(1); mipi_dsi_clk_enable(); /* make sure dsi_cmd_mdp is idle */ mipi_dsi_cmd_mdp_busy(); } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #if defined(CONFIG_MDP_RUNTIME_BANDWIDTH) #else #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif #endif mipi_dsi_clk_disable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); mipi_dsi_ahb_ctrl(0); mipi_dsi_unprepare_clocks(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("End of %s ....:\n", __func__); bmipi_off = 1; } }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; #ifdef CONFIG_HUAWEI_KERNEL struct mipi_panel_info *mipi; unsigned int datamask = 0; #endif mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_HUAWEI_KERNEL mipi = &mfd->panel_info.mipi; if (mipi->data_lane3) datamask |= 1<<3; if (mipi->data_lane2) datamask |= 1<<2; if (mipi->data_lane1) datamask |= 1<<1; if (mipi->data_lane0) datamask |= 1<<0; MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask ); mdelay(1); MIPI_OUTP(MIPI_DSI_BASE + 0xA8, datamask|(1<<4)); mdelay(1); #endif #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; //#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) #if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) struct mipi_panel_info *mipi; #endif mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); //#if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_VEGAPVW) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) #if defined(CONFIG_MACH_MSM8960_CHEETAH) || defined(CONFIG_MACH_MSM8960_SIRIUSLTE)|| defined(CONFIG_MACH_MSM8960_EF44S) || defined(CONFIG_MACH_MSM8960_MAGNUS) mipi = &mfd->panel_info.mipi; if (mipi->force_clk_lane_hs) { u32 tmp; tmp = MIPI_INP(MIPI_DSI_BASE + 0xA8); tmp &= ~(1<<28); MIPI_OUTP(MIPI_DSI_BASE + 0xA8, tmp); wmb(); printk("[MIPI: shinbrad Low speed Clk Set(Off Sequence) .................................................]\n"); } #endif /* * Description: dsi clock is need to perform shutdown. * mdp4_dsi_cmd_dma_busy_wait() will enable dsi clock if disabled. * also, wait until dma (overlay and dmap) finish. */ if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (mdp_rev >= MDP_REV_41) { mdp4_dsi_cmd_dma_busy_wait(mfd); mdp4_dsi_blt_dmap_busy_wait(mfd); mipi_dsi_mdp_busy_wait(mfd); } else { mdp3_dsi_cmd_dma_busy_wait(mfd); } } else { /* video mode, wait until fifo cleaned */ #if !defined(CONFIG_MACH_MSM8960_MAGNUS) mipi_dsi_controller_cfg(0); #endif } /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ #if defined (CONFIG_MACH_MSM8960_MAGNUS) ret = panel_next_off(pdev); mipi_dsi_controller_cfg(0); #else mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #endif #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif local_bh_disable(); mipi_dsi_clk_disable(); local_bh_enable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); local_bh_disable(); mipi_dsi_ahb_ctrl(0); local_bh_enable(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); pr_debug("%s-:\n", __func__); return ret; }
int mdp_lcdc_on(struct platform_device *pdev) { int lcdc_width; int lcdc_height; int lcdc_bpp; int lcdc_border_clr; int lcdc_underflow_clr; int lcdc_hsync_skew; int hsync_period; int hsync_ctrl; int vsync_period; int display_hctl; int display_v_start; int display_v_end; int active_hctl; int active_h_start; int active_h_end; int active_v_start; int active_v_end; int ctrl_polarity; int h_back_porch; int h_front_porch; int v_back_porch; int v_front_porch; int hsync_pulse_width; int vsync_pulse_width; int hsync_polarity; int vsync_polarity; int data_en_polarity; int hsync_start_x; int hsync_end_x; uint8 *buf; int bpp, ptype; struct fb_info *fbi; struct fb_var_screeninfo *var; struct msm_fb_data_type *mfd; struct mdp4_overlay_pipe *pipe; int ret; mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev); if (!mfd) return -ENODEV; if (mfd->key != MFD_KEY) return -EINVAL; fbi = mfd->fbi; var = &fbi->var; /* MDP cmd block enable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE); if (is_mdp4_hw_reset()) { mdp4_hw_init(); outpdw(MDP_BASE + 0x0038, mdp4_display_intf); } bpp = fbi->var.bits_per_pixel / 8; buf = (uint8 *) fbi->fix.smem_start; buf += fbi->var.xoffset * bpp + fbi->var.yoffset * fbi->fix.line_length; if (lcdc_pipe == NULL) { ptype = mdp4_overlay_format2type(mfd->fb_imgType); if (ptype < 0) printk(KERN_INFO "%s: format2type failed\n", __func__); pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0); if (pipe == NULL) printk(KERN_INFO "%s: pipe_alloc failed\n", __func__); pipe->pipe_used++; pipe->mixer_stage = MDP4_MIXER_STAGE_BASE; pipe->mixer_num = MDP4_MIXER0; pipe->src_format = mfd->fb_imgType; mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_LCDC); ret = mdp4_overlay_format2pipe(pipe); if (ret < 0) printk(KERN_INFO "%s: format2pipe failed\n", __func__); lcdc_pipe = pipe; /* keep it */ init_completion(&lcdc_comp); } else { pipe = lcdc_pipe; } pipe->src_height = fbi->var.yres; pipe->src_width = fbi->var.xres; pipe->src_h = fbi->var.yres; pipe->src_w = fbi->var.xres; pipe->src_y = 0; pipe->src_x = 0; pipe->srcp0_addr = (uint32) buf; pipe->srcp0_ystride = fbi->fix.line_length; mdp4_overlay_dmap_xy(pipe); mdp4_overlay_dmap_cfg(mfd, 1); mdp4_overlay_rgb_setup(pipe); mdp4_mixer_stage_up(pipe); mdp4_overlayproc_cfg(pipe); /* * LCDC timing setting */ h_back_porch = var->left_margin; h_front_porch = var->right_margin; v_back_porch = var->upper_margin; v_front_porch = var->lower_margin; hsync_pulse_width = var->hsync_len; vsync_pulse_width = var->vsync_len; lcdc_border_clr = mfd->panel_info.lcdc.border_clr; lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr; lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew; lcdc_width = var->xres; lcdc_height = var->yres; lcdc_bpp = mfd->panel_info.bpp; hsync_period = hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch; hsync_ctrl = (hsync_period << 16) | hsync_pulse_width; hsync_start_x = hsync_pulse_width + h_back_porch; hsync_end_x = hsync_period - h_front_porch - 1; display_hctl = (hsync_end_x << 16) | hsync_start_x; vsync_period = (vsync_pulse_width + v_back_porch + lcdc_height + v_front_porch) * hsync_period; display_v_start = (vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew; display_v_end = vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1; if (lcdc_width != var->xres) { active_h_start = hsync_start_x + first_pixel_start_x; active_h_end = active_h_start + var->xres - 1; active_hctl = ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start; } else { active_hctl = 0; } if (lcdc_height != var->yres) { active_v_start = display_v_start + first_pixel_start_y * hsync_period; active_v_end = active_v_start + (var->yres) * hsync_period - 1; active_v_start |= ACTIVE_START_Y_EN; } else { active_v_start = 0; active_v_end = 0; } #ifdef CONFIG_FB_MSM_MDP40 hsync_polarity = 1; vsync_polarity = 1; lcdc_underflow_clr |= 0x80000000; /* enable recovery */ #else hsync_polarity = 0; vsync_polarity = 0; #endif data_en_polarity = 0; ctrl_polarity = (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x4, hsync_ctrl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x8, vsync_period); MDP_OUTP(MDP_BASE + LCDC_BASE + 0xc, vsync_pulse_width * hsync_period); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x10, display_hctl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x14, display_v_start); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x18, display_v_end); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x28, lcdc_border_clr); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x2c, lcdc_underflow_clr); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x30, lcdc_hsync_skew); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x38, ctrl_polarity); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x1c, active_hctl); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x20, active_v_start); MDP_OUTP(MDP_BASE + LCDC_BASE + 0x24, active_v_end); mdp4_overlay_reg_flush(pipe, 1); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(2); #endif mdp_histogram_ctrl(TRUE); ret = panel_next_on(pdev); if (ret == 0) { /* enable LCDC block */ MDP_OUTP(MDP_BASE + LCDC_BASE, 1); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE); } /* MDP cmd block disable */ mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); return ret; }
static int mipi_dsi_off(struct platform_device *pdev) { int ret = 0; struct msm_fb_data_type *mfd; struct msm_panel_info *pinfo; mfd = platform_get_drvdata(pdev); pinfo = &mfd->panel_info; if (mdp_rev >= MDP_REV_41) mutex_lock(&mfd->dma->ov_mutex); else down(&mfd->dma->mutex); mdp4_overlay_dsi_state_set(ST_DSI_SUSPEND); /* make sure dsi clk is on so that * dcs commands can be sent */ mipi_dsi_clk_cfg(1); /* make sure dsi_cmd_mdp is idle */ mipi_dsi_cmd_mdp_busy(); /* * Desctiption: change to DSI_CMD_MODE since it needed to * tx DCS dsiplay off comamnd to panel */ mipi_dsi_op_mode_config(DSI_CMD_MODE); if (mfd->panel_info.type == MIPI_CMD_PANEL) { if (pinfo->lcd.vsync_enable) { if (pinfo->lcd.hw_vsync_mode && vsync_gpio >= 0) { if (MDP_REV_303 != mdp_rev) gpio_free(vsync_gpio); } mipi_dsi_set_tear_off(mfd); } } ret = panel_next_off(pdev); #ifdef CONFIG_MSM_BUS_SCALING mdp_bus_scale_update_request(0); #endif spin_lock_bh(&dsi_clk_lock); mipi_dsi_clk_disable(); /* disbale dsi engine */ MIPI_OUTP(MIPI_DSI_BASE + 0x0000, 0); mipi_dsi_phy_ctrl(0); mipi_dsi_ahb_ctrl(0); spin_unlock_bh(&dsi_clk_lock); mipi_dsi_unprepare_clocks(); if (mipi_dsi_pdata && mipi_dsi_pdata->dsi_power_save) mipi_dsi_pdata->dsi_power_save(0); if (mdp_rev >= MDP_REV_41) mutex_unlock(&mfd->dma->ov_mutex); else up(&mfd->dma->mutex); return ret; }