int mdp_edp_on(struct msm_panel_info *pinfo) { uint32_t ctl0_reg_val, ctl1_reg_val; mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); return NO_ERROR; }
int mdp_dma_on(struct msm_panel_info *pinfo) { uint32_t ctl0_reg_val, ctl1_reg_val; mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); writel(0x01, MDP_CTL_0_BASE + CTL_START); return NO_ERROR; }
int mdp_dsi_video_on(struct msm_panel_info *pinfo) { uint32_t ctl0_reg_val, ctl1_reg_val; uint32_t timing_engine_en; mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split) writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); if (pinfo->dest == DISPLAY_1) timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN; else timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN; writel(0x01, timing_engine_en + mdss_mdp_intf_offset()); return NO_ERROR; }