示例#1
0
文件: mdp5.c 项目: sndnvaps/lk-1
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
	int ret = NO_ERROR;
	uint32_t left_pipe, right_pipe;

	mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE);
	mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);

	mdp_clk_gating_ctrl();
	mdss_vbif_setup();

	mdss_smp_setup(pinfo, left_pipe, right_pipe);

	mdss_qos_remapper_setup();

	mdss_source_pipe_config(fb, pinfo, left_pipe);
	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	if (pinfo->lcdc.dual_pipe)
		writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP);
	else
		writel(0x40, MDP_CTL_0_BASE + CTL_TOP);

	writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL);
	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);

	return ret;
}
示例#2
0
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
	uint32_t left_pipe, right_pipe;
	dprintf(SPEW, "ENTER: %s\n", __func__);

	mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset());
	pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB;
	mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);

	mdp_clk_gating_ctrl();
	mdss_vbif_setup();

	mdss_smp_setup(pinfo, left_pipe, right_pipe);

	mdss_qos_remapper_setup();

	mdss_source_pipe_config(fb, pinfo, left_pipe);
	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	if (pinfo->lcdc.dual_pipe)
		writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP);
	else
		writel(0x40, MDP_CTL_0_BASE + CTL_TOP);

	writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL);
	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);

	return 0;
}
示例#3
0
文件: mdp5.c 项目: sndnvaps/lk-1
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
		struct fbcon_config *fb)
{
	int ret = NO_ERROR;
	uint32_t intf_sel = 0x100;
	uint32_t left_pipe, right_pipe;
	uint32_t reg;

	mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
	mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE);

	if (pinfo->mipi.dual_dsi) {
		mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE);
		mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE);
	}

	mdp_clk_gating_ctrl();

	mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
	mdss_vbif_setup();
	mdss_smp_setup(pinfo, left_pipe, right_pipe);

	mdss_qos_remapper_setup();
	mdss_vbif_qos_remapper_setup(pinfo);

	mdss_source_pipe_config(fb, pinfo, left_pipe);

	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
	writel(reg, MDP_CTL_0_BASE + CTL_TOP);

	/*If dst_split is enabled only intf 2 needs to be enabled.
	CTL_1 path should not be set since CTL_0 itself is going
	to split after DSPP block*/
	if (pinfo->fbc.enabled)
		mdss_fbc_cfg(pinfo);

	if (pinfo->mipi.dual_dsi) {
		if (!pinfo->lcdc.dst_split) {
			reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0);
			writel(reg, MDP_CTL_1_BASE + CTL_TOP);
		}
		intf_sel |= BIT(16); /* INTF 2 enable */
	}

	writel(intf_sel, MDP_DISP_INTF_SEL);

	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);

	return ret;
}
示例#4
0
int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
	int ret = NO_ERROR;
	struct lcdc_panel_info *lcdc = NULL;
	uint32_t left_pipe, right_pipe;

	mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);

	switch (pinfo->pipe_type) {
		case MDSS_MDP_PIPE_TYPE_RGB:
			left_pipe = MDP_VP_0_RGB_0_BASE;
			right_pipe = MDP_VP_0_RGB_1_BASE;
			break;
		case MDSS_MDP_PIPE_TYPE_DMA:
			left_pipe = MDP_VP_0_DMA_0_BASE;
			right_pipe = MDP_VP_0_DMA_1_BASE;
			break;
		case MDSS_MDP_PIPE_TYPE_VIG:
		default:
			left_pipe = MDP_VP_0_VIG_0_BASE;
			right_pipe = MDP_VP_0_VIG_1_BASE;
			break;
	}

	mdp_clk_gating_ctrl();

	mdss_vbif_setup();
	mdss_smp_setup(pinfo, left_pipe, right_pipe);

	mdss_qos_remapper_setup();

	mdss_source_pipe_config(fb, pinfo, left_pipe);
	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	if (pinfo->lcdc.dual_pipe)
		writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP);
	else
		writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP);

	writel(0x9, MDP_DISP_INTF_SEL);
	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);

	return 0;
}
示例#5
0
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
                struct fbcon_config *fb)
{
	uint32_t intf_sel = BIT(8);
	int ret = NO_ERROR;
	uint32_t left_pipe, right_pipe;

	struct lcdc_panel_info *lcdc = NULL;
	uint32_t mdss_mdp_intf_off = 0;

	if (pinfo == NULL)
		return ERR_INVALID_ARGS;

	lcdc =  &(pinfo->lcdc);
	if (lcdc == NULL)
		return ERR_INVALID_ARGS;

	if (pinfo->lcdc.split_display) {
		writel(0x102, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
		writel(0x2, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
		writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
	}

	mdss_mdp_intf_off = mdss_mdp_intf_offset();

	mdp_clk_gating_ctrl();

	if (pinfo->mipi.dual_dsi)
		intf_sel |= BIT(16); /* INTF 2 enable */

	writel(intf_sel, MDP_DISP_INTF_SEL);

	switch (pinfo->pipe_type) {
		case MDSS_MDP_PIPE_TYPE_RGB:
			left_pipe = MDP_VP_0_RGB_0_BASE;
			right_pipe = MDP_VP_0_RGB_1_BASE;
			break;
		case MDSS_MDP_PIPE_TYPE_DMA:
			left_pipe = MDP_VP_0_DMA_0_BASE;
			right_pipe = MDP_VP_0_DMA_1_BASE;
			break;
		case MDSS_MDP_PIPE_TYPE_VIG:
		default:
			left_pipe = MDP_VP_0_VIG_0_BASE;
			right_pipe = MDP_VP_0_VIG_1_BASE;
			break;
	}

	mdss_vbif_setup();
	mdss_smp_setup(pinfo, left_pipe, right_pipe);
	mdss_qos_remapper_setup();

	mdss_source_pipe_config(fb, pinfo, left_pipe);

	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
	writel(0x21f20, MDP_CTL_0_BASE + CTL_TOP);

	if (pinfo->mipi.dual_dsi) {
		writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
		writel(0x21F30, MDP_CTL_1_BASE + CTL_TOP);
	}

	return ret;
}
示例#6
0
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
		struct fbcon_config *fb)
{
	int ret = NO_ERROR;
	struct lcdc_panel_info *lcdc = NULL;
	uint32_t intf_sel = 0x100;
	uint32_t left_pipe, right_pipe;

	mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
	mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE);

	if (pinfo->mipi.dual_dsi) {
		mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE);
		mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE);
	}

	mdp_clk_gating_ctrl();

	switch (pinfo->pipe_type) {
		case MDSS_MDP_PIPE_TYPE_RGB:
			left_pipe = MDP_VP_0_RGB_0_BASE;
			right_pipe = MDP_VP_0_RGB_1_BASE;
			break;
		case MDSS_MDP_PIPE_TYPE_DMA:
			left_pipe = MDP_VP_0_DMA_0_BASE;
			right_pipe = MDP_VP_0_DMA_1_BASE;
			break;
		case MDSS_MDP_PIPE_TYPE_VIG:
		default:
			left_pipe = MDP_VP_0_VIG_0_BASE;
			right_pipe = MDP_VP_0_VIG_1_BASE;
			break;
	}

	mdss_vbif_setup();
	mdss_smp_setup(pinfo, left_pipe, right_pipe);

	mdss_qos_remapper_setup();

	mdss_source_pipe_config(fb, pinfo, left_pipe);

	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP);

	/*If dst_split is enabled only intf 2 needs to be enabled.
	CTL_1 path should not be set since CTL_0 itself is going
	to split after DSPP block*/

	if (pinfo->mipi.dual_dsi) {
		if (!pinfo->lcdc.dst_split)
			writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP);
		intf_sel |= BIT(16); /* INTF 2 enable */
	}

	writel(intf_sel, MDP_DISP_INTF_SEL);

	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);

	return 0;
}
示例#7
0
文件: mdp5.c 项目: sndnvaps/lk-1
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
                struct fbcon_config *fb)
{
	uint32_t intf_sel = BIT(8);
	uint32_t reg;
	int ret = NO_ERROR;
	uint32_t left_pipe, right_pipe;

	struct lcdc_panel_info *lcdc = NULL;
	uint32_t mdss_mdp_intf_off = 0;

	if (pinfo == NULL)
		return ERR_INVALID_ARGS;

	lcdc =  &(pinfo->lcdc);
	if (lcdc == NULL)
		return ERR_INVALID_ARGS;

	if (pinfo->lcdc.split_display) {
		reg = BIT(1); /* Command mode */
		if (pinfo->lcdc.pipe_swap)
			reg |= BIT(4); /* Use intf2 as trigger */
		else
			reg |= BIT(8); /* Use intf1 as trigger */
		writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
		writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
		writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
	}

	mdss_mdp_intf_off = mdss_mdp_intf_offset();

	mdp_clk_gating_ctrl();

	if (pinfo->mipi.dual_dsi)
		intf_sel |= BIT(16); /* INTF 2 enable */

	writel(intf_sel, MDP_DISP_INTF_SEL);

	mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
	mdss_vbif_setup();
	mdss_smp_setup(pinfo, left_pipe, right_pipe);
	mdss_qos_remapper_setup();
	mdss_vbif_qos_remapper_setup(pinfo);

	mdss_source_pipe_config(fb, pinfo, left_pipe);

	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
	reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
	writel(reg, MDP_CTL_0_BASE + CTL_TOP);

	if (pinfo->fbc.enabled)
		mdss_fbc_cfg(pinfo);

	if (pinfo->mipi.dual_dsi) {
		writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
		reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
		writel(reg, MDP_CTL_1_BASE + CTL_TOP);
	}

	return ret;
}
示例#8
0
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
                struct fbcon_config *fb)
{
	uint32_t intf_sel, sintf_sel;
	uint32_t intf_base, sintf_base;
	uint32_t reg;
	int ret = NO_ERROR;
	uint32_t left_pipe, right_pipe;

	struct lcdc_panel_info *lcdc = NULL;

	if (pinfo == NULL)
		return ERR_INVALID_ARGS;

	lcdc =  &(pinfo->lcdc);
	if (lcdc == NULL)
		return ERR_INVALID_ARGS;

	mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);

	if (pinfo->lcdc.split_display) {
		reg = BIT(1); /* Command mode */
		if (pinfo->lcdc.dst_split)
			reg |= BIT(2); /* Enable SMART_PANEL_FREE_RUN mode */
		if (pinfo->lcdc.pipe_swap)
			reg |= BIT(4); /* Use intf2 as trigger */
		else
			reg |= BIT(8); /* Use intf1 as trigger */
		writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
		writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
		writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
	}

	if (pinfo->lcdc.dst_split) {
		uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
		writel(BIT(16) | BIT(20) | BIT(21), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
		writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
	}

	mdp_clk_gating_ctrl();

	if (pinfo->mipi.dual_dsi)
		intf_sel |= sintf_sel; /* INTF 2 enable */

	writel(intf_sel, MDP_DISP_INTF_SEL);

	mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
	mdss_vbif_setup();
	mdss_smp_setup(pinfo, left_pipe, right_pipe);
	mdss_qos_remapper_setup();
	mdss_vbif_qos_remapper_setup(pinfo);

	mdss_source_pipe_config(fb, pinfo, left_pipe);

	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	writel(0x213F, MDP_PANEL_FORMAT + intf_base);
	reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
	writel(reg, MDP_CTL_0_BASE + CTL_TOP);

	if (pinfo->fbc.enabled)
		mdss_fbc_cfg(pinfo);

	if (pinfo->mipi.dual_dsi) {
		writel(0x213F, sintf_base + MDP_PANEL_FORMAT);
		if (!pinfo->lcdc.dst_split) {
			reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
			writel(reg, MDP_CTL_1_BASE + CTL_TOP);
		}
	}

	return ret;
}
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
		struct fbcon_config *fb)
{
	uint32_t intf_sel, sintf_sel;
	uint32_t intf_base, sintf_base;
	uint32_t left_pipe, right_pipe;
	uint32_t reg;

	mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);

	mdss_intf_tg_setup(pinfo, intf_base);
	mdss_intf_fetch_start_config(pinfo, intf_base);

	if (pinfo->mipi.dual_dsi) {
		mdss_intf_tg_setup(pinfo, sintf_base);
		mdss_intf_fetch_start_config(pinfo, sintf_base);
	}

	mdp_clk_gating_ctrl();

	mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
	mdss_vbif_setup();
	if (!has_fixed_size_smp())
		mdss_smp_setup(pinfo, left_pipe, right_pipe);

	mdss_qos_remapper_setup();
	mdss_vbif_qos_remapper_setup(pinfo);

	mdss_source_pipe_config(fb, pinfo, left_pipe);

	if (pinfo->lcdc.dual_pipe)
		mdss_source_pipe_config(fb, pinfo, right_pipe);

	mdss_layer_mixer_setup(fb, pinfo);

	reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1);

	/* enable 3D mux for dual_pipe but single interface config */
	if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi &&
		!pinfo->lcdc.split_display)
		reg |= BIT(19) | BIT(20);

	writel(reg, MDP_CTL_0_BASE + CTL_TOP);

	/*If dst_split is enabled only intf 2 needs to be enabled.
	CTL_1 path should not be set since CTL_0 itself is going
	to split after DSPP block*/
	if (pinfo->fbc.enabled)
		mdss_fbc_cfg(pinfo);

	if (pinfo->mipi.dual_dsi) {
		if (!pinfo->lcdc.dst_split) {
			reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0);
			writel(reg, MDP_CTL_1_BASE + CTL_TOP);
		}
		intf_sel |= sintf_sel; /* INTF 2 enable */
	}

	writel(intf_sel, MDP_DISP_INTF_SEL);

	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);

	return 0;
}