static void reset(int hard) { reg = 0; mmc3_init(sync); mem_setwrite(6,write67); mem_setwrite(7,write67); }
static void reset(int hard) { write4 = mem_getwrite(4); mem_setwrite(4,write45); mem_setwrite(5,write45); reg = 0; sync(); }
static void reset(int hard) { latch_init(sync); mem_setwrite(6,latch_write); mem_setwrite(7,latch_write); mem_setprg16(0x8,0); mem_setprg16(0xC,0xFF); }
static void mapper45_init(int hard) { mmc3_init(mapper45_sync); write6 = mem_getwrite(6); mem_setwrite(6,mapper45_write); mem_setwrite(7,mapper45_write); reg[0] = reg[1] = reg[2] = reg[3] = 0; regindex = 0; }
static void init(int hard) { int i; mem_setwrite(0x9,write_low); for(i=0xC;i<0x10;i++) mem_setwrite(i,write_high); reg[0] = reg[1] = 0; sync(); }
void vrc6_init(int revision) { int i; mem_setwrite(0x8,write_8000); mem_setwrite(0x9,write_9000); mem_setwrite(0xA,write_A000); mem_setwrite(0xB,write_B000); mem_setwrite(0xC,write_C000); mem_setwrite(0xD,write_D000); mem_setwrite(0xE,write_E000); mem_setwrite(0xF,write_F000); if(revision == KONAMI_VRC6B) { nes_setsramsize(2); mem_setsram8(0x6,0); } prg[0] = 0; prg[1] = -2; for(i=0; i>8; i++) chr[i] = 0; mirror = 0; irqlatch = 0; irqenabled = 0; irqcounter = 0; apu_setext(nes->apu,&vrc6); sync(); }
void mmc5_init(int hard) { mem_setwrite(5,mmc5_write); prgsize = 0; prgselect = 0; mmc5_sync(); }
static void mapper44_init(int hard) { mmc3_init(sync); reg = 0; writeA = mem_getwrite(0xA); mem_setwrite(0xA,mapper44_write); sync(); }
void nes_reset(int hard) { int i; if(nes->rom == 0) return; //set default read/write handlers for(i=0;i<16;i++) { mem_setread(i,0); mem_setwrite(i,0); } //set rom read handlers (mappers might use these) for(i=8;i<16;i++) mem_setread(i,nes_read_rom); //ram mem_setreadptr(0,nes->ram); mem_setwriteptr(0,nes->ram); mem_setreadptr(1,nes->ram); mem_setwriteptr(1,nes->ram); //ppu mem_setread(2,ppu_read); mem_setwrite(2,ppu_write); mem_setread(3,ppu_read); mem_setwrite(3,ppu_write); //apu mem_setread(4,nes_read_4000); mem_setwrite(4,nes_write_4000); //mapper will set its read/write handlers nes->mapper->reset(hard); nes->frame_irqmode = 0; apu_reset(hard); ppu_reset(); dead6502_reset(); if(hard) { memset(nes->ram,0,0x800); for(i=0;i<32;i++) pal_write(i,startup_pal[i]); } log_message("nes reset ok\n"); }
void mapper90_init(int r) { int i; mem_setread(0x5,mapper90_read_mul); mem_setwrite(0x5,mapper90_write_mul); mem_setwrite(0x8,mapper90_write_prg); mem_setwrite(0x9,mapper90_write_chrlo); mem_setwrite(0xA,mapper90_write_chrhi); mem_setwrite(0xB,mapper90_write_nt); mem_setwrite(0xC,mapper90_write_irq); mem_setwrite(0xD,mapper90_write_control); for(i=0;i<8;i++) { prg[i & 3] = 0; chrlo[i] = 0; chrhi[i] = 0; nt[i & 3] = 0; } bankmode = 0; mul[0] = mul[1] = 0; onebyte = 0; irqenabled = 0; irqmode = 0; irqxor = 0; irqlo = irqhi = 0; mirror = 0; revision = r; syncprg(); syncchr(); syncnt(); }
static void reset(int hard) { int i; for(i=6;i<0x10;i++) mem_setwrite(i,write); reg[0] = reg[1] = 0; sync(); }
static void reset(int hard) { int i; write4 = mem_getwrite(4); for(i=8;i<16;i++) mem_setwrite(i,write_upper); reg = 0; sync(); }
static void reset(int hard) { int i; write4 = mem_getwrite(4); mem_setwrite(4,write_4000); for(i=8;i<0x10;i++) mem_setwrite(i,write); nes_setsramsize(2); mem_setsram8(6,0); prg[0] = 0; prg[1] = 1; prg[2] = 0xFE; prg[3] = 0xFF; for(i=0;i<8;i++) chr[i] = i; mirror = MIRROR_V; irqenabled = 0; irqcycles = 0; sync(); }
static void init(int hard) { int i; for(i=8;i<16;i++) mem_setwrite(i,write_upper); for(i=0;i<6;i++) { prg[i & 1] = 0; chr[i] = 0; } sync(); }
void mmc2_init(int hard) { int i; for(i=8;i<0x10;i++) mem_setwrite(i,mmc2_write); LatchA[0] = LatchA[1] = 0; LatchB[0] = LatchB[1] = 0; LatchAState = LatchBState = 0; PRGBank = 0; Mirroring = 0; mmc2_sync(); }
void fme7_init(int hard) { int i; for(i=0x8;i<0xA;i++) mem_setwrite(i,fme7_write_command); for(i=0xA;i<0xC;i++) mem_setwrite(i,fme7_write_data); for(i=0xC;i<0x10;i++) mem_setwrite(i,fme7_write_sound); for(i=0;i<8;i++) { prg[i & 3] = i & 3; chr[i] = i; } nes_setsramsize(2); command = 0; mirror = 0; irqcounter = 0; irqenabled = 0; apu_setext(nes->apu,&fme7); fme7_sync(); }
static void reset(int hard) { int i; for(i=8;i<0x10;i++) mem_setwrite(i,write_upper); prg = 0; for(i=0;i<4;i++) chr[i] = 0; mirror = 0; irqenabled = irqwrite = 0; irqcounter = 0; sync(); }
void vrc1_init(int hard) { int i; for(i=8;i<0x10;i++) mem_setwrite(i,vrc1_write); prg[0] = 0; prg[1] = 0; prg[2] = 0; chr[0] = 0; chr[1] = 0; mirror = 0; sync(); }
void irem_h3001_init(int hard) { int i; for(i=8;i<0x10;i++) mem_setwrite(i,write_reg); prg[0] = 0; prg[1] = 1; prg[2] = -2; for(i=0;i<8;i++) chr[i] = i; irqcounter = 0; irqenabled = 0; mirror = 0; sync(); }
void vrc2_init(int revision) { int i; switch(revision) { default: case KONAMI_VRC2A: map = vrc2a_map; break; case KONAMI_VRC2B: map = vrc2b_map; break; } for(i=8;i<0x10;i++) mem_setwrite(i,write_vrc2); for(i=0;i<8;i++) { prg[i & 1] = 0; chr[i] = 0; } mirror = 0; sync(); }