/*******************************************************************************
* driverConfig
*
* DESCRIPTION:
* This function initializes the driver level of the quarterDeck software.
*
* INPUTS:
* None.
* OUTPUTS:
* None.
* RETURNS:
* GT_OK - on success, or
* GT_OUT_OF_CPU_MEM - if failed to allocate CPU memory,
* GT_FAIL - otherwise.
*
* COMMENTS:
* 1. This function should perform the following:
* - Initialize the global switch configuration structure.
* - Initialize Mii Interface
*
*******************************************************************************/
GT_STATUS driverConfig
(
IN GT_QD_DEV *dev
)
{
GT_U16 deviceId;
GT_BOOL highSmiDevAddr;
if(dev->accessMode == SMI_AUTO_SCAN_MODE)
{
/* Initialize the MII / SMI interface, search for the device */
if((deviceId = miiSmiIfInit(dev,&highSmiDevAddr)) == 0)
{
return GT_FAIL;
}
dev->baseRegAddr = (highSmiDevAddr)?0x10:0;
}
else
{
if((deviceId = miiSmiManualIfInit(dev,(GT_U32)dev->baseRegAddr)) == 0)
{
return GT_FAIL;
}
}
/* Init the device's config struct. */
dev->deviceId = deviceId >> 4;
dev->revision = (GT_U8)deviceId & 0xF;
return GT_OK;
}
/*******************************************************************************
* driverConfig
*
* DESCRIPTION:
* This function initializes the driver level of the quarterDeck software.
*
* INPUTS:
* None.
* OUTPUTS:
* None.
* RETURNS:
* GT_OK - on success, or
* GT_OUT_OF_CPU_MEM - if failed to allocate CPU memory,
* GT_FAIL - otherwise.
*
* COMMENTS:
* 1. This function should perform the following:
* - Initialize the global switch configuration structure.
* - Initialize Mii Interface
*
*******************************************************************************/
GT_STATUS driverConfig
(
IN GT_QD_DEV *dev
)
{
GT_U16 deviceId;
#ifdef CONFIG_ARCH_FEROCEON_KW
GT_U16 tmp, phy;
#endif
GT_BOOL highSmiDevAddr;
if(dev->accessMode == SMI_AUTO_SCAN_MODE)
{
/* Initialize the MII / SMI interface, search for the device */
if((deviceId = miiSmiIfInit(dev,&highSmiDevAddr)) == 0)
{
return GT_FAIL;
}
dev->baseRegAddr = (highSmiDevAddr)?0x10:0;
}
else
{
if((deviceId = miiSmiManualIfInit(dev,(GT_U32)dev->baseRegAddr)) == 0)
{
return GT_FAIL;
}
}
/* Init the device's config struct. */
dev->deviceId = deviceId >> 4;
dev->revision = (GT_U8)deviceId & 0xF;
#ifdef CONFIG_ARCH_FEROCEON_KW
if(mvBoardIdGet() == RD_88F6281A_ID) {
/* Enable RGMII delay on Tx and Rx for CPU port */
miiSmiIfWriteRegister(dev, 0x14,0x1a, 0x81e7);
miiSmiIfReadRegister(dev, 0x15,0x1a,&tmp);
miiSmiIfWriteRegister(dev, 0x15,0x1a,0x18);
miiSmiIfWriteRegister(dev, 0x14,0x1a,0xc1e7);
/* swap MDI signals for PHYs 0,1,2,3,4 on RD_88F6281A_ID */
for(phy = 0; phy < 5; phy++) {
miiSmiIfWriteRegister(dev, 0x1c,0x19,0xf);
miiSmiIfWriteRegister(dev, 0x1c,0x18,(0x9414 + (phy*0x20)));
miiSmiIfReadRegister(dev, 0x1c, 0x19,&tmp); /* used for delay */
/* testing - read phy register #20
miiSmiIfWriteRegister(dev, 0x1c,0x18,(0x9814+ (phy*0x20)));
miiSmiIfReadRegister(dev, 0x1c, 0x19,&tmp);
DBG_INFO(("phy-%d reg20 = 0x%x\n",phy,tmp));
*/
}
}
#endif
return GT_OK;
}
