int board_eth_init(bd_t *bis) { ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; /* * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting * is not correct. */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_mdio(FM1_DTSEC1, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_mdio(FM1_DTSEC2, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); #ifdef CONFIG_FMAN_ENET cpu_eth_init(bis); #endif return pci_eth_init(bis); }
static int super_hydra_mdio_init(char *realbusname, char *fakebusname) { struct super_hydra_mdio *hmdio; struct mii_dev *bus = mdio_alloc(); if (!bus) { printf("Failed to allocate Hydra MDIO bus\n"); return -1; } hmdio = malloc(sizeof(*hmdio)); if (!hmdio) { printf("Failed to allocate Hydra private data\n"); free(bus); return -1; } bus->read = super_hydra_mdio_read; bus->write = super_hydra_mdio_write; bus->reset = super_hydra_mdio_reset; strcpy(bus->name, fakebusname); hmdio->realbus = miiphy_get_dev_by_name(realbusname); if (!hmdio->realbus) { printf("No bus with name %s\n", realbusname); free(bus); free(hmdio); return -1; } bus->priv = hmdio; return mdio_register(bus); }
static int bcm_sf2_eth_init(struct eth_device *dev) { struct eth_info *eth = (struct eth_info *)(dev->priv); struct eth_dma *dma = &(eth->dma); struct phy_device *phydev; int rc = 0; int i; rc = eth->mac_init(dev); if (rc) { error("%s: Couldn't cofigure MAC!\n", __func__); return rc; } /* disable DMA */ dma->disable_dma(dma, MAC_DMA_RX); dma->disable_dma(dma, MAC_DMA_TX); eth->port_num = 0; debug("Connecting PHY 0...\n"); phydev = phy_connect(miiphy_get_dev_by_name(dev->name), 0, dev, eth->phy_interface); if (phydev != NULL) { eth->port[0] = phydev; eth->port_num += 1; } else { debug("No PHY found for port 0\n"); } for (i = 0; i < eth->port_num; i++) phy_config(eth->port[i]); return rc; }
int pch_gbe_probe(struct udevice *dev) { struct pch_gbe_priv *priv; struct eth_pdata *plat = dev_get_platdata(dev); void *iobase; /* * The priv structure contains the descriptors and frame buffers which * need a strict buswidth alignment (64 bytes). This is guaranteed by * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER. */ priv = dev_get_priv(dev); priv->dev = dev; iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM); plat->iobase = (ulong)iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; /* Read MAC address from SROM and initialize dev->enetaddr with it */ pch_gbe_mac_read(priv->mac_regs, plat->enetaddr); plat->phy_interface = PHY_INTERFACE_MODE_RGMII; pch_gbe_mdio_init(dev->name, priv->mac_regs); priv->bus = miiphy_get_dev_by_name(dev->name); return pch_gbe_phy_init(dev); }
static int ls1021a_mdio_init(char *realbusname, char *fakebusname) { struct ls1021a_mdio *lsmdio; struct mii_dev *bus = mdio_alloc(); if (!bus) { printf("Failed to allocate LS102xA MDIO bus\n"); return -1; } lsmdio = malloc(sizeof(*lsmdio)); if (!lsmdio) { printf("Failed to allocate LS102xA private data\n"); free(bus); return -1; } bus->read = ls1021a_mdio_read; bus->write = ls1021a_mdio_write; bus->reset = ls1021a_mdio_reset; sprintf(bus->name, fakebusname); lsmdio->realbus = miiphy_get_dev_by_name(realbusname); if (!lsmdio->realbus) { printf("No bus with name %s\n", realbusname); free(bus); free(lsmdio); return -1; } bus->priv = lsmdio; return mdio_register(bus); }
static int t1024qds_mdio_init(char *realbusname, u8 muxval) { struct t1024qds_mdio *pmdio; struct mii_dev *bus = mdio_alloc(); if (!bus) { printf("Failed to allocate t1024qds MDIO bus\n"); return -1; } pmdio = malloc(sizeof(*pmdio)); if (!pmdio) { printf("Failed to allocate t1024qds private data\n"); free(bus); return -1; } bus->read = t1024qds_mdio_read; bus->write = t1024qds_mdio_write; bus->reset = t1024qds_mdio_reset; strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval)); pmdio->realbus = miiphy_get_dev_by_name(realbusname); if (!pmdio->realbus) { printf("No bus with name %s\n", realbusname); free(bus); free(pmdio); return -1; } pmdio->muxval = muxval; bus->priv = pmdio; return mdio_register(bus); }
static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev) { struct mii_dev *mii; mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME); /* find & connect PHY */ priv->phydev = phy_connect(mii, priv->phy_addr, dev, priv->phyif); if (!priv->phydev) { printf("%s: %s: Error, PHY connect\n", __FILE__, __func__); return 0; } /* Wait for phy to complete reset */ mdelay(10); /* configure supported modes */ priv->phydev->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | SUPPORTED_Autoneg; priv->phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | ADVERTISED_Autoneg; priv->phydev->autoneg = AUTONEG_ENABLE; return 0; }
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; struct eth_device *netdev; u32 ncfgr; macb = malloc(sizeof(struct macb_device)); if (!macb) { printf("Error: Failed to allocate memory for MACB%d\n", id); return -1; } memset(macb, 0, sizeof(struct macb_device)); netdev = &macb->netdev; macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, &macb->rx_buffer_dma); macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->rx_ring_dma); macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc), &macb->tx_ring_dma); macb->regs = regs; macb->phy_addr = phy_addr; if (macb_is_gem(macb)) sprintf(netdev->name, "gmac%d", id); else sprintf(netdev->name, "macb%d", id); netdev->init = macb_init; netdev->halt = macb_halt; netdev->send = macb_send; netdev->recv = macb_recv; netdev->write_hwaddr = macb_write_hwaddr; /* * Do some basic initialization so that we at least can talk * to the PHY */ if (macb_is_gem(macb)) { ncfgr = gem_mdc_clk_div(id, macb); ncfgr |= GEM_BF(DBW, 1); } else { ncfgr = macb_mdc_clk_div(id, macb); } macb_writel(macb, NCFGR, ncfgr); eth_register(netdev); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); macb->bus = miiphy_get_dev_by_name(netdev->name); #endif return 0; }
static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) { struct mii_dev *bus = miiphy_get_dev_by_name(name); struct super_hydra_mdio *priv = bus->priv; priv->mask = mask; priv->val = val; }
int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr, int phy_addr, u32 emio) { struct eth_device *dev; struct zynq_gem_priv *priv; void *bd_space; dev = calloc(1, sizeof(*dev)); if (dev == NULL) return -1; dev->priv = calloc(1, sizeof(struct zynq_gem_priv)); if (dev->priv == NULL) { free(dev); return -1; } priv = dev->priv; /* Align rxbuffers to ARCH_DMA_MINALIGN */ priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); /* Align bd_space to MMU_SECTION_SHIFT */ bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, DCACHE_OFF); /* Initialize the bd spaces for tx and rx bd's */ priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((unsigned long)bd_space + BD_SEPRN_SPACE); priv->phyaddr = phy_addr; priv->emio = emio; #ifndef CONFIG_ZYNQ_GEM_INTERFACE priv->interface = PHY_INTERFACE_MODE_MII; #else priv->interface = CONFIG_ZYNQ_GEM_INTERFACE; #endif sprintf(dev->name, "Gem.%lx", base_addr); dev->iobase = base_addr; dev->init = zynq_gem_init; dev->halt = zynq_gem_halt; dev->send = zynq_gem_send; dev->recv = zynq_gem_recv; dev->write_hwaddr = zynq_gem_setup_mac; eth_register(dev); miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write); priv->bus = miiphy_get_dev_by_name(dev->name); return 1; }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; unsigned int i; printf("Initializing Fman\n"); /* Register the real 1G MDIO bus */ dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR); fm_info_set_mdio(FIRST_PORT, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR); fm_info_set_mdio(SECOND_PORT, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); /* Never disable DTSEC1 - it controls MDIO */ for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); } #ifdef CONFIG_PPC_P5040 for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { if (!IS_VALID_PORT(i)) fm_disable_port(i); } #endif cpu_eth_init(bis); cyrus_phy_tuning(FIRST_PORT_ADDR); cyrus_phy_tuning(SECOND_PORT_ADDR); #endif return pci_eth_init(bis); }
int ccdc_eth_init(void) { uint k; uint octo_phy_mask = 0; int ret; struct mii_dev *bus; /* Init SoC's phys */ bus = miiphy_get_dev_by_name("ethernet@34000"); if (bus) init_host_phys(bus); bus = miiphy_get_dev_by_name("ethernet@70000"); if (bus) init_host_phys(bus); /* Init octo phys */ octo_phy_mask = calculate_octo_phy_mask(); printf("IHS PHYS: %08x", octo_phy_mask); ret = init_octo_phys(octo_phy_mask); if (ret) return ret; printf("\n"); if (!get_fpga()) { puts("fpga was NULL\n"); return 1; } /* reset all FPGA-QSGMII instances */ for (k = 0; k < 80; ++k) writel(1 << 31, get_fpga()->qsgmii_port_state[k]); udelay(100); for (k = 0; k < 80; ++k) writel(0, get_fpga()->qsgmii_port_state[k]); return 0; }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; int phy_addr = 0; printf("Initializing Fman\n"); memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); /* * Program on board RGMII, SGMII PHY addresses. */ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { #ifdef CONFIG_T1040RDB case PHY_INTERFACE_MODE_SGMII: /* T1040RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: fm_info_set_phy_address(i, 0); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); } cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int pch_gbe_register(bd_t *bis) { struct eth_device *dev; struct pch_gbe_priv *priv; pci_dev_t devno; u32 iobase; devno = pci_find_devices(supported, 0); if (devno == -1) return -ENODEV; dev = (struct eth_device *)malloc(sizeof(*dev)); if (!dev) return -ENOMEM; memset(dev, 0, sizeof(*dev)); /* * The priv structure contains the descriptors and frame buffers which * need a strict buswidth alignment (64 bytes) */ priv = (struct pch_gbe_priv *)memalign(PCH_GBE_ALIGN_SIZE, sizeof(*priv)); if (!priv) { free(dev); return -ENOMEM; } memset(priv, 0, sizeof(*priv)); dev->priv = priv; priv->dev = dev; priv->bdf = devno; pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; iobase = pci_mem_to_phys(devno, iobase); dev->iobase = iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; sprintf(dev->name, "pch_gbe.%x", iobase); /* Read MAC address from SROM and initialize dev->enetaddr with it */ pch_gbe_mac_read(priv->mac_regs, dev->enetaddr); dev->init = pch_gbe_init; dev->halt = pch_gbe_halt; dev->send = pch_gbe_send; dev->recv = pch_gbe_recv; eth_register(dev); priv->interface = PHY_INTERFACE_MODE_RGMII; pch_gbe_mdio_init(dev->name, priv->mac_regs); priv->bus = miiphy_get_dev_by_name(dev->name); return pch_gbe_phy_init(dev); }
/* Initialize device structure. Returns success if PHY * initialization succeeded (i.e. if it recognizes the PHY) */ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) { struct eth_device *dev; int i; struct tsec_private *priv; dev = (struct eth_device *)malloc(sizeof *dev); if (NULL == dev) return 0; memset(dev, 0, sizeof *dev); priv = (struct tsec_private *)malloc(sizeof(*priv)); if (NULL == priv) return 0; privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; sprintf(dev->name, tsec_info->devname); priv->interface = tsec_info->interface; priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); dev->iobase = 0; dev->priv = priv; dev->init = tsec_init; dev->halt = tsec_halt; dev->send = tsec_send; dev->recv = tsec_recv; #ifdef CONFIG_MCAST_TFTP dev->mcast = tsec_mcast_addr; #endif /* Tell u-boot to get the addr from the env */ for (i = 0; i < 6; i++) dev->enetaddr[i] = 0; eth_register(dev); /* Reset the MAC */ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); /* Try to initialize PHY here, and return */ return init_phy(dev); }
static int sh_eth_phy_config(struct sh_eth_dev *eth) { int port = eth->port, ret = 0; struct sh_eth_info *port_info = ð->port_info[port]; struct eth_device *dev = port_info->dev; struct phy_device *phydev; phydev = phy_connect(miiphy_get_dev_by_name(dev->name), port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII); port_info->phydev = phydev; phy_config(phydev); return ret; }
static int pic32_eth_remove(struct udevice *dev) { struct pic32eth_dev *priv = dev_get_priv(dev); struct mii_dev *bus; dm_gpio_free(dev, &priv->rst_gpio); phy_shutdown(priv->phydev); free(priv->phydev); bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME); mdio_unregister(bus); mdio_free(bus); iounmap(priv->ectl_regs); return 0; }
int board_eth_init(bd_t *bis) { u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR; ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; /* * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting * is not correct. */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_mdio(FM1_DTSEC1, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_mdio(FM1_DTSEC2, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); /* Make SERDES connected to SGMII by cleaing bcsr19[7] */ if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) clrbits_8(&bcsr[19], BCSR19_SGMII_SEL_L); #ifdef CONFIG_FMAN_ENET cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; struct eth_device *netdev; macb = malloc(sizeof(struct macb_device)); if (!macb) { printf("Error: Failed to allocate memory for MACB%d\n", id); return -1; } memset(macb, 0, sizeof(struct macb_device)); netdev = &macb->netdev; macb->regs = regs; macb->phy_addr = phy_addr; if (macb_is_gem(macb)) sprintf(netdev->name, "gmac%d", id); else sprintf(netdev->name, "macb%d", id); netdev->init = macb_init; netdev->halt = macb_halt; netdev->send = macb_send; netdev->recv = macb_recv; netdev->write_hwaddr = macb_write_hwaddr; _macb_eth_initialize(macb); eth_register(netdev); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) int retval; struct mii_dev *mdiodev = mdio_alloc(); if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); mdiodev->read = macb_miiphy_read; mdiodev->write = macb_miiphy_write; retval = mdio_register(mdiodev); if (retval < 0) return retval; macb->bus = miiphy_get_dev_by_name(netdev->name); #endif return 0; }
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr, unsigned long dma_addr) { struct eth_device *dev; struct axidma_priv *priv; dev = calloc(1, sizeof(struct eth_device)); if (dev == NULL) return -1; dev->priv = calloc(1, sizeof(struct axidma_priv)); if (dev->priv == NULL) { free(dev); return -1; } priv = dev->priv; sprintf(dev->name, "aximac.%lx", base_addr); dev->iobase = base_addr; priv->dmatx = (struct axidma_reg *)dma_addr; /* RX channel offset is 0x30 */ priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30); dev->init = axiemac_init; dev->halt = axiemac_halt; dev->send = axiemac_send; dev->recv = axiemac_recv; dev->write_hwaddr = axiemac_setup_mac; #ifdef CONFIG_PHY_ADDR priv->phyaddr = CONFIG_PHY_ADDR; #else priv->phyaddr = -1; #endif eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write); priv->bus = miiphy_get_dev_by_name(dev->name); priv->bus->reset = axiemac_bus_reset; #endif return 1; }
struct mii_dev *mii_dev_for_muxval(u8 muxval) { struct mii_dev *bus; const char *name = t1040_qds_mdio_name_for_muxval(muxval); if (!name) { printf("No bus for muxval %x\n", muxval); return NULL; } bus = miiphy_get_dev_by_name(name); if (!bus) { printf("No bus by name %s\n", name); return NULL; } return bus; }
static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus, struct phy_device **phydev, int *addrlo, int *addrhi) { struct phy_device *dev = *phydev; if ((argc < 1) || (argc > 2)) return -1; /* If there are two arguments, it's busname addr */ if (argc == 2) { *bus = miiphy_get_dev_by_name(argv[0]); if (!*bus) return -1; return extract_range(argv[1], addrlo, addrhi); } /* It must be one argument, here */ /* * This argument can be one of two things: * 1) Ethernet device name * 2) Just an address (use the previously-used bus) * * We check all buses for a PHY which is connected to an ethernet * device by the given name. If none are found, we call * extract_range() on the string, and see if it's an address range. */ dev = mdio_phydev_for_ethname(argv[0]); if (dev) { *addrlo = *addrhi = dev->addr; *bus = dev->bus; return 0; } /* It's an address or nothing useful */ return extract_range(argv[0], addrlo, addrhi); }
static int macb_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct macb_device *macb = dev_get_priv(dev); const char *phy_mode; __maybe_unused int ret; phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); if (phy_mode) macb->phy_interface = phy_get_interface_by_name(phy_mode); if (macb->phy_interface == -1) { debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); return -EINVAL; } macb->regs = (void *)pdata->iobase; #ifdef CONFIG_CLK ret = macb_enable_clk(dev); if (ret) return ret; #endif _macb_eth_initialize(macb); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) macb->bus = mdio_alloc(); if (!macb->bus) return -ENOMEM; strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); macb->bus->read = macb_miiphy_read; macb->bus->write = macb_miiphy_write; ret = mdio_register(macb->bus); if (ret < 0) return ret; macb->bus = miiphy_get_dev_by_name(dev->name); #endif return 0; }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Set the on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); switch (srds_s1) { #ifdef CONFIG_T1024RDB case 0x95: /* set the on-board RGMII2 PHY */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); /* set 10G XFI with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; #endif case 0x6a: case 0x6b: case 0x77: case 0x135: /* set the on-board 2.5G SGMII AQR105 PHY */ fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR); #ifdef CONFIG_T1023RDB /* set the on-board 1G SGMII RTL8211F PHY */ fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR); #endif break; default: printf("SerDes protocol 0x%x is not supported on T102xRDB\n", srds_s1); break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; case PHY_INTERFACE_MODE_SGMII: #if defined(CONFIG_T1023RDB) dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); #elif defined(CONFIG_T1024RDB) dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); #endif fm_info_set_mdio(i, dev); break; case PHY_INTERFACE_MODE_SGMII_2500: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET int i; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; u32 srds_s1; struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); /* Set the two on-board SGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); /* Set the on-board AQ PHY address */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); switch (srds_s1) { case 0x1133: break; default: printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", srds_s1); break; } dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); /* XFI on lane A, MAC 9 */ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; struct mii_dev *bus; int qsgmii; int phy_real_addr; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int srds_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; printf("Initializing Fman\n"); initialize_lane_to_slot(); /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); memset(mdio_mux, 0, sizeof(mdio_mux)); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_tgec_mdio_init(bis, &tgec_mdio_info); /* Register the three virtual MDIO front-ends */ super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_RGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM1_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM2_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "SUPER_HYDRA_FM3_SGMII_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM1_TGEC_MDIO"); super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, "SUPER_HYDRA_FM2_TGEC_MDIO"); /* * Program the DTSEC PHY addresses assuming that they are all SGMII. * For any DTSEC that's RGMII, we'll override its PHY address later. * We assume that DTSEC5 is only used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); #if (CONFIG_SYS_NUM_FMAN == 2) fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); #endif switch (srds_prtcl) { case 0: case 3: case 4: case 6: case 0x11: case 0x2a: case 0x34: case 0x36: fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); break; case 1: case 2: case 5: case 7: case 0x35: fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); break; default: printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; debug("FM1@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); switch (slot) { case 1: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 3: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the * second on-board RGMII port. The other DTSECs cannot * be routed to RGMII. */ debug("FM1@DTSEC%u is RGMII at address %u\n", idx + 1, 0); fm_info_set_phy_address(i, 0); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"); qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM_FM1, REGNUM); if (qsgmii) { for (i = FM1_DTSEC1; i < FM1_DTSEC1 + PORT_NUM_FM1; i++) { if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) { phy_real_addr = PHY_BASE_ADDR + i - FM1_DTSEC1; fm_info_set_phy_address(i, phy_real_addr); } } switch (srds_prtcl) { case 0x00: case 0x03: case 0x04: case 0x06: case 0x11: case 0x2a: case 0x34: case 0x36: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 2); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 3); break; case 0x01: case 0x02: case 0x05: case 0x07: case 0x35: fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR + 0); fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); break; default: break; } } /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } fm_info_set_mdio(FM1_10GEC1, miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); #if (CONFIG_SYS_NUM_FMAN == 2) for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { int idx = i - FM2_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; debug("FM2@DTSEC%u expects SGMII in slot %u\n", idx + 1, slot); switch (slot) { case 1: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 3: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; if (i == FM2_DTSEC1 || i == FM2_DTSEC2) { super_hydra_mdio_set_mux( "SUPER_HYDRA_FM3_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name( "SUPER_HYDRA_FM3_SGMII_MDIO")); } else { super_hydra_mdio_set_mux( "SUPER_HYDRA_FM2_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name( "SUPER_HYDRA_FM2_SGMII_MDIO")); } break; case PHY_INTERFACE_MODE_RGMII: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the * second on-board RGMII port. The other DTSECs cannot * be routed to RGMII. */ debug("FM2@DTSEC%u is RGMII at address %u\n", idx + 1, 1); fm_info_set_phy_address(i, 1); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman2: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"); set_sgmii_phy(bus, FM2_DTSEC3, PORT_NUM_FM2, PHY_BASE_ADDR); bus = miiphy_get_dev_by_name("SUPER_HYDRA_FM3_SGMII_MDIO"); set_sgmii_phy(bus, FM2_DTSEC1, PORT_NUM_FM2, PHY_BASE_ADDR); /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM2); if (lane >= 0) { debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } fm_info_set_mdio(FM2_10GEC1, miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); #endif cpu_eth_init(bis); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) int i, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1; srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; dtsec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fm_memac_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the 10G MDIO bus */ fm_memac_mdio_init(bis, &tgec_mdio_info); /* Set the two on-board RGMII PHY address */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); switch (srds_s1) { case 0x66: case 0x6b: fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); break; default: printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", srds_s1); break; } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(i, dev); break; default: break; } } cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; int phy_addr = 0; #ifdef CONFIG_VSC9953 phy_interface_t phy_int; struct mii_dev *bus; #endif printf("Initializing Fman\n"); memac_mdio_info.regs = (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fm_memac_mdio_init(bis, &memac_mdio_info); /* * Program on board RGMII, SGMII PHY addresses. */ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: /* T1040RDB & T1040D4RDB only supports SGMII on * DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_T1042RDB case PHY_INTERFACE_MODE_SGMII: /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */ if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i)) fm_info_set_phy_address(i, 0); /* T1042RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_T1042D4RDB case PHY_INTERFACE_MODE_SGMII: /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 * & DTSEC3 */ if (FM1_DTSEC1 == i) phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; if (FM1_DTSEC2 == i) phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; if (FM1_DTSEC3 == i) phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; #endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: fm_info_set_phy_address(i, 0); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII || fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE) fm_info_set_mdio(i, NULL); else fm_info_set_mdio(i, miiphy_get_dev_by_name( DEFAULT_FM_MDIO_NAME)); } #ifdef CONFIG_VSC9953 /* SerDes configured for QSGMII */ if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { for (i = 0; i < 4; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; phy_int = PHY_INTERFACE_MODE_QSGMII; vsc9953_port_info_set_mdio(i, bus); vsc9953_port_info_set_phy_address(i, phy_addr); vsc9953_port_info_set_phy_int(i, phy_int); vsc9953_port_enable(i); } } if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { for (i = 4; i < 8; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; phy_int = PHY_INTERFACE_MODE_QSGMII; vsc9953_port_info_set_mdio(i, bus); vsc9953_port_info_set_phy_address(i, phy_addr); vsc9953_port_info_set_phy_int(i, phy_int); vsc9953_port_enable(i); } } /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */ if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0) vsc9953_port_enable(8); /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */ if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { /* Enable L2 On MAC2 using SCFG */ struct ccsr_scfg *scfg = (struct ccsr_scfg *) CONFIG_SYS_MPC85xx_SCFG; out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | (0x80000000)); vsc9953_port_enable(9); } #endif cpu_eth_init(bis); #endif return pci_eth_init(bis); }
/* * Initialize a single ll_temac devices * * Returns the result of ll_temac phy interface that were initialized */ int xilinx_ll_temac_initialize(bd_t *bis, struct ll_temac_info *devinf) { struct eth_device *dev; struct ll_temac *ll_temac; dev = calloc(1, sizeof(*dev)); if (dev == NULL) return 0; ll_temac = calloc(1, sizeof(struct ll_temac)); if (ll_temac == NULL) { free(dev); return 0; } /* use given name or generate its own unique name */ if (devinf->devname) { strncpy(dev->name, devinf->devname, sizeof(dev->name)); } else { snprintf(dev->name, sizeof(dev->name), "lltemac.%lx", devinf->base_addr); devinf->devname = dev->name; } dev->iobase = devinf->base_addr; dev->priv = ll_temac; dev->init = ll_temac_init; dev->halt = ll_temac_halt; dev->write_hwaddr = ll_temac_setup_mac_addr; ll_temac->ctrladdr = devinf->ctrl_addr; if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_PLB) { #if defined(CONFIG_XILINX_440) || defined(CONFIG_XILINX_405) if (devinf->flags & XILINX_LL_TEMAC_M_SDMA_DCR) { ll_temac_collect_xldcr_sdma_reg_addr(dev); ll_temac->in32 = ll_temac_xldcr_in32; ll_temac->out32 = ll_temac_xldcr_out32; } else #endif { ll_temac_collect_xlplb_sdma_reg_addr(dev); ll_temac->in32 = ll_temac_xlplb_in32; ll_temac->out32 = ll_temac_xlplb_out32; } ll_temac->ctrlinit = ll_temac_init_sdma; ll_temac->ctrlhalt = ll_temac_halt_sdma; ll_temac->ctrlreset = ll_temac_reset_sdma; dev->recv = ll_temac_recv_sdma; dev->send = ll_temac_send_sdma; } else { ll_temac->in32 = NULL; ll_temac->out32 = NULL; ll_temac->ctrlinit = NULL; ll_temac->ctrlhalt = NULL; ll_temac->ctrlreset = ll_temac_reset_fifo; dev->recv = ll_temac_recv_fifo; dev->send = ll_temac_send_fifo; } /* Link to specified MDIO bus */ strncpy(ll_temac->mdio_busname, devinf->mdio_busname, MDIO_NAME_LEN); ll_temac->bus = miiphy_get_dev_by_name(ll_temac->mdio_busname); /* Looking for a valid PHY address if it is not yet set */ if (devinf->phyaddr == -1) ll_temac->phyaddr = ll_temac_phy_addr(ll_temac->bus); else ll_temac->phyaddr = devinf->phyaddr; eth_register(dev); /* Try to initialize PHY here, and return */ return ll_temac_phy_init(dev); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; int lane; struct mii_dev *bus; printf("Initializing Fman\n"); initialize_lane_to_slot(); /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); memset(mdio_mux, 0, sizeof(mdio_mux)); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the real 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); tgec_mdio_info.regs = (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; /* Register the real 10G MDIO bus */ fm_tgec_mdio_init(bis, &tgec_mdio_info); /* Register the three virtual MDIO front-ends */ hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO"); hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO"); /* * Program the DTSEC PHY addresses assuming that they are all SGMII. * For any DTSEC that's RGMII, we'll override its PHY address later. * We assume that DTSEC5 is only used for RGMII. */ fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane < 0) break; slot = lane_to_slot[lane]; mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; switch (slot) { case 1: /* Always DTSEC5 on Bank 3 */ mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | BRDCFG1_EMI1_EN; break; case 2: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | BRDCFG1_EMI1_EN; break; case 5: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | BRDCFG1_EMI1_EN; break; case 6: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | BRDCFG1_EMI1_EN; break; case 7: mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | BRDCFG1_EMI1_EN; break; }; hydra_mdio_set_mux("HYDRA_SGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: /* * If DTSEC4 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC5 is RGMII, * then it's routed via via EC2 to the second on-board * RGMII port. The other DTSECs cannot be routed to * RGMII. */ fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1); mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN; hydra_mdio_set_mux("HYDRA_RGMII_MDIO", mdio_mux[i].mask, mdio_mux[i].val); fm_info_set_mdio(i, miiphy_get_dev_by_name("HYDRA_RGMII_MDIO")); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", idx + 1, fm_info_get_enet_if(i)); fm_info_set_phy_address(i, 0); break; } } bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"); set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR); /* * For 10G, we only support one XAUI card per Fman. If present, then we * force its routing and never touch those bits again, which removes the * need for Linux to do any muxing. This works because of the way * BRDCFG1 is defined, but it's a bit hackish. * * The PHY address for the XAUI card depends on which slot it's in. The * macros we use imply that the PHY address is based on which FM, but * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, * and FM2 could only use a XAUI in slot 4. On the Hydra board, we * check the actual slot and just use the macros as-is, even though * the P3041 and P5020 only have one Fman. */ lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { slot = lane_to_slot[lane]; if (slot == 1) { /* XAUI card is in slot 1 */ clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, BRDCFG1_EMI2_SEL_SLOT1); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); } else { /* XAUI card is in slot 2 */ clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK, BRDCFG1_EMI2_SEL_SLOT2); fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); } } fm_info_set_mdio(FM1_10GEC1, miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); cpu_eth_init(bis); #endif return pci_eth_init(bis); }