void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
spin_lock_irqsave(&mdp_spin_lock, flag);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
mfd->dma->busy_pid = (current->pid << 16)+__LINE__;
if (dsi_pipe->blt_addr) {
mfd->dma->dmap_busy = TRUE;
mfd->dma->dmap_pid = (current->pid << 16)+__LINE__;
}
wmb(); /* make sure all registers updated */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
wmb();
if (pipe->blt_addr == 0) {
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger();
}
}
/*
* mdp4_dmap_done_dsi: called from isr
* DAM_P_DONE only used when blt enabled
*/
void mdp4_dma_p_done_dsi(struct mdp_dma_data *dma)
{
int diff;
spin_lock(&mdp_done_lock);
mdp_disable_irq_nosync(MDP_DMA2_TERM); /* disable intr */
spin_lock(&mdp_spin_lock);
dsi_pipe->dmap_cnt++;
diff = dsi_pipe->ov_cnt - dsi_pipe->dmap_cnt;
#ifdef BLTDEBUG
printk(KERN_INFO "%s: ov_cnt=%d dmap_cnt=%d\n", __func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt);
#endif
if (diff <= 0) {
dma->dmap_busy = FALSE;
dma->dmap_pid = __LINE__;
complete(&dma->dmap_comp);
if (dsi_pipe->blt_end) {
dsi_pipe->blt_end = 0;
dsi_pipe->blt_addr = 0;
wmb();
#ifdef BLTDEBUG
PR_DISP_INFO("%s(%d): END, ov_cnt=%d dmap_cnt=%d\n", __func__, __LINE__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt);
#endif
mdp_intr_mask &= ~INTR_DMA_P_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
}
spin_unlock(&mdp_spin_lock);
spin_unlock(&mdp_done_lock);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
return;
}
dma->busy = FALSE;
dma->busy_pid = __LINE__;
spin_unlock(&mdp_spin_lock);
complete(&dma->comp);
if (atomic_read(&busy_wait_cnt))
atomic_dec(&busy_wait_cnt);
mdp4_blt_xy_update(dsi_pipe);
mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */
spin_unlock(&mdp_done_lock);
#ifdef BLTDEBUG
printk(KERN_INFO "%s: kickoff dmap\n", __func__);
#endif
/* kick off dmap */
outpdw(MDP_BASE + 0x000c, 0x0);
wmb();
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger();
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
}
/*
* mdp4_overlay0_done_dsi_cmd: called from isr
*/
void mdp4_overlay0_done_dsi_cmd(struct mdp_dma_data *dma)
{
int diff;
mdp_disable_irq_nosync(MDP_OVERLAY0_TERM);
spin_lock(&mdp_spin_lock);
rmb();
if (dsi_pipe->blt_addr == 0) {
dma->busy = FALSE;
complete(&dma->comp);
if (atomic_read(&busy_wait_cnt))
atomic_dec(&busy_wait_cnt);
spin_unlock(&mdp_spin_lock);
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
return;
}
/* blt enabled */
if (dsi_pipe->blt_end == 0)
dsi_pipe->ov_cnt++;
#ifdef BLTDEBUG
printk("%s: ov_cnt=%d dmap_cnt=%d\n", __func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt);
#endif
if (dsi_pipe->blt_cnt == 0) {
/* first kickoff since blt enabled */
mdp_intr_mask |= INTR_DMA_P_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
}
dsi_pipe->blt_cnt++;
diff = dsi_pipe->ov_cnt - dsi_pipe->dmap_cnt;
if (diff >= 2) {
spin_unlock(&mdp_spin_lock);
return;
}
dma->busy = FALSE;
dma->dmap_busy = TRUE;
complete(&dma->comp);
if (atomic_read(&busy_wait_cnt))
atomic_dec(&busy_wait_cnt);
spin_unlock(&mdp_spin_lock);
mdp4_blt_xy_update(dsi_pipe);
mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */
#ifdef BLTDEBUG
printk("%s: kickoff dmap\n", __func__);
#endif
/* kick off dmap */
outpdw(MDP_BASE + 0x000c, 0x0);
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger();
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
/* start OVERLAY pipe */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger();
}
/*
* mdp4_dmap_done_dsi: called from isr
* DAM_P_DONE only used when blt enabled
*/
void mdp4_dma_p_done_dsi(struct mdp_dma_data *dma)
{
int diff;
mdp_disable_irq_nosync(MDP_DMA2_TERM); /* disable intr */
dsi_pipe->dmap_cnt++;
diff = dsi_pipe->ov_cnt - dsi_pipe->dmap_cnt;
pr_debug("%s: ov_cnt=%d dmap_cnt=%d\n",
__func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt);
if (diff <= 0) {
spin_lock(&mdp_spin_lock);
dma->dmap_busy = FALSE;
complete(&dma->dmap_comp);
spin_unlock(&mdp_spin_lock);
if (dsi_pipe->blt_end) {
dsi_pipe->blt_end = 0;
dsi_pipe->blt_addr = 0;
pr_debug("%s: END, ov_cnt=%d dmap_cnt=%d\n",
__func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt);
mdp_intr_mask &= ~INTR_DMA_P_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
}
return;
}
spin_lock(&mdp_spin_lock);
dma->busy = FALSE;
spin_unlock(&mdp_spin_lock);
complete(&dma->comp);
if (busy_wait_cnt)
busy_wait_cnt--;
pr_debug("%s: kickoff dmap\n", __func__);
mdp4_blt_xy_update(dsi_pipe);
mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */
/* kick off dmap */
outpdw(MDP_BASE + 0x000c, 0x0);
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger();
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
spin_lock_irqsave(&mdp_spin_lock, flag);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
if (dsi_pipe->blt_addr)
mfd->dma->dmap_busy = TRUE;
/* start OVERLAY pipe */
spin_unlock_irqrestore(&mdp_spin_lock, flag);
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
if (pipe->blt_addr == 0) {
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger();
}
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
down(&mfd->sem);
mfd->dma->busy = TRUE;
INIT_COMPLETION(dsi_cmd_comp);
mdp_enable_irq(MDP_OVERLAY0_TERM);
/* Kick off overlay engine */
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger();
up(&mfd->sem);
/* wait until DMA finishes the current job */
wait_for_completion_killable(&dsi_cmd_comp);
mdp_disable_irq(MDP_OVERLAY0_TERM);
}
void mdp4_dsi_cmd_overlay_kickoff(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe)
{
unsigned long flag;
/* change mdp clk */
mdp4_set_perf_level();
#ifndef MDP4_DSI_SW_TRIGGER
mipi_dsi_mdp_busy_wait(mfd);
if (dsi_pipe->blt_addr == 0)
mipi_dsi_cmd_mdp_start();
#endif
mdp4_overlay_dsi_state_set(ST_DSI_PLAYING);
spin_lock_irqsave(&mdp_spin_lock, flag);
mdp_enable_irq(MDP_OVERLAY0_TERM);
mfd->dma->busy = TRUE;
if (dsi_pipe->blt_addr)
mfd->dma->dmap_busy = TRUE;
/* start OVERLAY pipe */
wmb();
spin_unlock_irqrestore(&mdp_spin_lock, flag);
mdp_pipe_kickoff(MDP_OVERLAY0_TERM, mfd);
wmb();
mdp4_stat.kickoff_ov0++;
#ifdef MDP4_DSI_SW_TRIGGER
if (dsi_pipe->blt_addr == 0) {
/* trigger dsi cmd engine */
mipi_dsi_cmd_mdp_sw_trigger(mfd);
}
#endif
}
void mdp_pipe_kickoff(uint32 term, struct msm_fb_data_type *mfd)
{
/* complete all the writes before starting */
wmb();
/* kick off PPP engine */
if (term == MDP_PPP_TERM) {
if (mdp_debug[MDP_PPP_BLOCK])
jiffies_to_timeval(jiffies, &mdp_ppp_timeval);
/* let's turn on PPP block */
mdp_pipe_ctrl(MDP_PPP_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
mdp_enable_irq(term);
INIT_COMPLETION(mdp_ppp_comp);
mdp_ppp_waiting = TRUE;
outpdw(MDP_BASE + 0x30, 0x1000);
wait_for_completion_killable(&mdp_ppp_comp);
mdp_disable_irq(term);
if (mdp_debug[MDP_PPP_BLOCK]) {
struct timeval now;
jiffies_to_timeval(jiffies, &now);
mdp_ppp_timeval.tv_usec =
now.tv_usec - mdp_ppp_timeval.tv_usec;
MSM_FB_DEBUG("MDP-PPP: %d\n",
(int)mdp_ppp_timeval.tv_usec);
}
} else if (term == MDP_DMA2_TERM) {
if (mdp_debug[MDP_DMA2_BLOCK]) {
MSM_FB_DEBUG("MDP-DMA2: %d\n",
(int)mdp_dma2_timeval.tv_usec);
jiffies_to_timeval(jiffies, &mdp_dma2_timeval);
}
/* DMA update timestamp */
mdp_dma2_last_update_time = ktime_get_real();
/* let's turn on DMA2 block */
#if 0
mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
#endif
#ifdef CONFIG_FB_MSM_MDP22
outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x0044, 0x0);/* start DMA */
#else
mdp_lut_enable();
#ifdef CONFIG_FB_MSM_MDP40
outpdw(MDP_BASE + 0x000c, 0x0); /* start DMA */
#else
outpdw(MDP_BASE + 0x0044, 0x0); /* start DMA */
#ifdef CONFIG_FB_MSM_MDP303
#ifdef CONFIG_FB_MSM_MIPI_DSI
mipi_dsi_cmd_mdp_sw_trigger();
#endif
#endif
#endif
#endif
#ifdef CONFIG_FB_MSM_MDP40
} else if (term == MDP_DMA_S_TERM) {
mdp_pipe_ctrl(MDP_DMA_S_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
outpdw(MDP_BASE + 0x0010, 0x0); /* start DMA */
} else if (term == MDP_DMA_E_TERM) {
mdp_pipe_ctrl(MDP_DMA_E_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
outpdw(MDP_BASE + 0x0014, 0x0); /* start DMA */
} else if (term == MDP_OVERLAY0_TERM) {
mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
mdp_lut_enable();
outpdw(MDP_BASE + 0x0004, 0);
} else if (term == MDP_OVERLAY1_TERM) {
mdp_pipe_ctrl(MDP_OVERLAY1_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
mdp_lut_enable();
outpdw(MDP_BASE + 0x0008, 0);
}
#else
} else if (term == MDP_DMA_S_TERM) {
