int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
{
switch (size)
{
case 1:
return mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t*)buf);
case 2:
return mips32_pracc_write_mem16(ejtag_info, addr, count,(uint16_t*)buf);
case 4:
if (count == 1)
return mips32_pracc_write_u32(ejtag_info, addr, (uint32_t*)buf);
else
return mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t*)buf);
}
return ERROR_OK;
}
int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
{
int retval;
switch (size) {
case 1:
retval = mips32_pracc_write_mem8(ejtag_info, addr, count, (uint8_t *)buf);
break;
case 2:
retval = mips32_pracc_write_mem16(ejtag_info, addr, count, (uint16_t *)buf);
break;
case 4:
if (count == 1)
retval = mips32_pracc_write_u32(ejtag_info, addr, (uint32_t *)buf);
else
retval = mips32_pracc_write_mem32(ejtag_info, addr, count, (uint32_t *)buf);
break;
default:
retval = ERROR_FAIL;
}
/**
* If we are in the cachable regoion and cache is activated,
* we must clean D$ + invalidate I$ after we did the write,
* so that changes do not continue to live only in D$, but to be
* replicated in I$ also (maybe we wrote the istructions)
*/
uint32_t conf = 0;
int cached = 0;
mips32_cp0_read(ejtag_info, &conf, 16, 0);
switch (KSEGX(addr)) {
case KUSEG:
cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT;
break;
case KSEG0:
cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT;
break;
case KSEG1:
/* uncachable segment - nothing to do */
break;
case KSEG2:
case KSEG3:
cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT;
break;
default:
/* what ? */
break;
}
/**
* Check cachablitiy bits coherency algorithm -
* is the region cacheable or uncached.
* If cacheable we have to synchronize the cache
*/
if (cached == 0x3) {
uint32_t start_addr, end_addr;
uint32_t rel;
start_addr = addr;
end_addr = addr + count * size;
/** select cache synchronisation mechanism based on Architecture Release */
rel = (conf & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
switch (rel) {
case MIPS32_ARCH_REL1:
/* MIPS32/64 Release 1 - we must use cache instruction */
mips32_pracc_clean_invalidate_cache(ejtag_info, start_addr, end_addr);
break;
case MIPS32_ARCH_REL2:
/* MIPS32/64 Release 2 - we can use synci instruction */
mips32_pracc_sync_cache(ejtag_info, start_addr, end_addr);
break;
default:
/* what ? */
break;
}
}
