void dio_init(){
dirHandle = mmap_device_io(PORT_LENGTH, DIR_ADDRESS);
portHandle = mmap_device_io(PORT_LENGTH, PORT_A_ADDRESS);
// Set port A as output.
out8(dirHandle, in8(dirHandle) & ~PORT_A_DIR_BIT);
out8(portHandle, value);
}
// Called once at startup
int nand_init(struct etfs_devio *dev) {
struct chipio *cio = dev->cio;
uintptr_t base;
uint32_t cfg7;
/* Map in the device registers */
base = cio->gpmc_vbase = mmap_device_io(OMAP3530_GPMC_SIZE, cio->gpmc_pbase);
if (base == (uintptr_t) MAP_FAILED)
dev->log(_SLOG_CRITICAL, "Unable to map in device registers (%d).", errno);
cio->gpmc_nand_vbase = base + (cio->cs * 0x30);
cfg7 = in32(cio->gpmc_nand_vbase + OMAP2420_GPMC_CS0+OMAP2420_GPMC_CONFIG7);
if (!(cfg7 & (1 << 6))) {
dev->log(_SLOG_CRITICAL, "Chip select %d is not enabled (%d).", cio->cs, errno);
return -1;
}
if(cio->cfg==0){
/*
* (1<<4) WRITEPROTECT is high
* (0<<0) NANDFORCEPOSTEDWRITE is off
*/
*OMAP_GPMC_CONFIG = (1<<4) | (0<<0);
}
return (0);
}
Input::Input(EventQueue *queue) {
this->myQueue = queue;
this-> done = false;
ctrlIBHandle = mmap_device_io(IO_PORT_SIZE, DATA_PORT_B);
pthread_create(&input, NULL, &inputHelper, this);
}
/* ______________________________________________________________________ */
int
main( )
{
int privity_err;
uintptr_t ctrl_handle_portC;
uintptr_t ctrl_handle_portB;
uintptr_t ctrl_handle_portCTL;
struct timespec my_timer_value;
my_timer_value.tv_nsec = 100000000;
/* Give this thread root permissions to access the hardware */
privity_err = ThreadCtl( _NTO_TCTL_IO, NULL );
if ( privity_err == -1 )
{
fprintf( stderr, "can't get root permissions\n" );
return -1;
}
/* Get a handle to the DIO port's Control register */
//ctrl_handle_portA = mmap_device_io( PORT_LENGTH, DIO_BASE_ADDR + 0x08 );
ctrl_handle_portB = mmap_device_io( PORT_LENGTH, DIO_BASE_ADDR + DIO_PORTB_ADDR);
ctrl_handle_portCTL = mmap_device_io( PORT_LENGTH, DIO_BASE_ADDR + DIO_CTL_ADDR);
/* Initialise the DIO port */
out8( ctrl_handle_portCTL, 0x00 );
//out8( ctrl_handle_portA, ENABLE_IN );
//out8( ctrl_handle_portB, ENABLE_OUT );
for (;;)
{
//out8( ctrl_handle_portB, HIGH );
out8( ctrl_handle_portB, HIGH );
nanospin( &my_timer_value );
//out8( ctrl_handle_portB, LOW );
out8( ctrl_handle_portB, LOW );
nanospin( &my_timer_value );
}
return 0;
}
/*
* IOControl constructor - initializes I/O settings and controls
*/
IOControl::IOControl( std::queue<Event>* qin, pthread_mutex_t *aQ ) {
// Initialize variables
accessQ = aQ;
q = qin;
// Initialize HW I/O control handlers
if( ThreadCtl(_NTO_TCTL_IO, NULL) == -1 )
{
std::perror("Error - could not access I/O registers");
}
CONTROL_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_CONTROL_REGISTER);
A_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_A_REGISTER);
B_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_B_REGISTER);
C_HANDLE = mmap_device_io(IO_PORT_SIZE, IO_C_REGISTER);
if(CONTROL_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map control register";
}
if(A_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map register A";
}
if(B_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map register B";
}
if(C_HANDLE == MAP_DEVICE_FAILED)
{
std::cout << "Failed to map register C";
}
// Initialize control register
// A is input
// B,C are output
out8(CONTROL_HANDLE,0x90);
}
int main(int argc, char *argv[]) {
int privity_err;
uintptr_t ctrl_handle;
uintptr_t data_handle;
int count;
struct timespec my_timer_value;
my_timer_value.tv_nsec = 500000;
/* Give this thread root permissions to access the hardware */
privity_err = ThreadCtl( _NTO_TCTL_IO, NULL );
if ( privity_err == -1 )
{
fprintf( stderr, "can't get root permissions\n" );
return -1;
}
/* Get a handle to the parallel port's Control register */
ctrl_handle = mmap_device_io( PORT_LENGTH, CTRL_ADDRESS );
/* Initialise the parallel port */
out8( ctrl_handle, INIT_BIT );
/* Get a handle to the parallel port's Data register */
data_handle = mmap_device_io( PORT_LENGTH, DATA_ADDRESS );
while(1)
{
/* Output a byte of lows to the data lines */
out8( data_handle, HIGH );
nanospin( &my_timer_value );
/* Output a byte of highs to the data lines */
out8( data_handle, LOW );
nanospin( &my_timer_value );
}
return 0;
}
int get_chip_type()
{
uintptr_t port = mmap_device_io( 4, OMAP_CONTROL_ID_CODE);
if (port == MAP_DEVICE_FAILED) {
return 0;
}
uint32_t chip_type = in32(port);
if (chip_type == OMAP5430_CONTROL_ID_CODE || chip_type == OMAP5432_CONTROL_ID_CODE){
rm_l4per_uart1_context = RM_L4PER_UART1_CONTEXT_OMAP5;
rm_l4per_uart2_context = RM_L4PER_UART2_CONTEXT_OMAP5;
rm_l4per_uart3_context = RM_L4PER_UART3_CONTEXT_OMAP5;
rm_l4per_uart4_context = RM_L4PER_UART4_CONTEXT_OMAP5;
}
munmap_device_io(port, 4);
return 1;
}
int main(int argc, char *argv[]) {
int privity_err;
uintptr_t ctrl_handle_chennalReg;
uintptr_t ctrl_handle_Inputgain;
uintptr_t ctrl_handle_commandRegMSB;
uintptr_t ctrl_handle_commandRegLSB;
uintptr_t ctrl_handle_portA;
int LSB, MSB, DATA;
struct timespec my_timer_value;
my_timer_value.tv_nsec = 10000; //10us
/* Give this thread root permissions to access the hardware */
privity_err = ThreadCtl( _NTO_TCTL_IO, NULL );
if ( privity_err == -1 )
{
fprintf( stderr, "can't get root permissions\n" );
return -1;
}
ctrl_handle_commandRegLSB = mmap_device_io( PORT_LENGTH, BASE_ADDR);
ctrl_handle_commandRegMSB = mmap_device_io( PORT_LENGTH, BASE_ADDR+1);
ctrl_handle_chennalReg = mmap_device_io( PORT_LENGTH, BASE_ADDR + 2);
ctrl_handle_Inputgain = mmap_device_io( PORT_LENGTH, BASE_ADDR + 3);
ctrl_handle_portA = mmap_device_io( PORT_LENGTH, BASE_ADDR + 8);
ctrl_handle_DIO = mmap_device_io(PORT_LENGTH, BASE_ADDR + B);
out8(ctrl_handle_chennalReg, 0xF0);
// Set Analog Input as -5V to +5V
out8( ctrl_handle_Inputgain, 0x01 );
int port_value = in8(ctrl_handle_Inputgain);
while (port_value & 0x20)
{
//nanospin( &my_timer_value );
port_value = in8(ctrl_handle_Inputgain);
}
out8(ctrl_handle_commandRegLSB, 0x80);
while (in8(ctrl_handle_Inputgain) & 0x80);
LSB = in8(ctrl_handle_commandRegLSB);
MSB = in8(ctrl_handle_commandRegMSB);
DATA = MSB*256 + LSB;
printf("Welcome to the QNX Momentics IDE\n");
return EXIT_SUCCESS;
}
///// 制御ボードイニシャライズ関数//////////////////////////////////////////////
void Board_Open(void)
{
int ch;
ThreadCtl(_NTO_TCTL_IO,0);
mmap_device_io(BIO_SIZE,0x300);
///// カウンタ初期化 /////
out8(Count_com,0x13); //A-2-phase x4
out8(Count_com,0x1b); //B-2-phase x4
out8(Count_com,0x14); //A-count enable set
out8(Count_com,0x1c); //B-count enable set
out8(Count_com,0x16); //separate mode
out8(Count_com,0x0e); //level CLR
out8(Count_com,0x0f); //edge CLR
for(ch=1; ch<=Channel; ch++){
M[ch].AD_Init = 2048; //とりあえずのADの初期値
DA_Write(ch,2048); //2.5V出力
}
}
int
omap_clock_toggle_init(DEV_OMAP* dev)
{
if (OMAP_UART1_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART1_CLKCTRL;
} else if (OMAP_UART2_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART2_CLKCTRL;
} else if (OMAP_UART3_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART3_CLKCTRL;
} else if (OMAP_UART4_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART4_CLKCTRL;
} else if (OMAP5_UART5_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART5_CLKCTRL;
} else if (OMAP5_UART6_PHYSBASE == dev->physbase) {
dev->clkctrl_phys = CM_L4PER_UART6_CLKCTRL;
} else {
dev->clkctrl_phys = 0;
dev->clkctrl_base = 0;
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "%s: Unrecognized physical address, clock toggling not enabled", __FUNCTION__);
return -1;
}
if (dev->clkctrl_phys) {
dev->clkctrl_base = mmap_device_io(4, dev->clkctrl_phys);
if (dev->clkctrl_base == (uintptr_t)MAP_FAILED) {
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "%s: mmap_device_io clkctrl_base: %s", __FUNCTION__, strerror(errno));
return -1;
}
}
/* Indicate clocks are disabled by default */
dev->idle = 1;
/* oband notification set to off */
dev->signal_oband_notification = 0;
/* initialize UART context */
omap_uart_ctx_init(dev);
return 0;
}
qmm10xt_typ *qmm10xt_init( unsigned base)
{
qmm10xt_typ *pboard;
if( (pboard = (qmm10xt_typ *) MALLOC( sizeof( qmm10xt_typ ))) == NULL )
return( NULL );
printf("Preparing to map QMM board at %03x\n", base);
fflush(stdout);
ThreadCtl(_NTO_TCTL_IO, NULL); /// required to access I/O ports
pboard->base = mmap_device_io(8, base); //maps 8 bytes of device space
printf("QMM board mapped, base 0x%x\n", base);
fflush(stdout);
pboard->error = 0;
pboard->dig_old_bits= 0;
QMM10XT_INT_DISABLE(pboard);
if( (pboard->ptimer[0] = am9513_init( base + CTS9513_1, TRUE )) == NULL )
{
FREE( pboard );
return( NULL );
}
if( (pboard->ptimer[1] = am9513_init( base + CTS9513_2, TRUE )) == NULL )
{
am9513_done( pboard->ptimer[0] );
FREE( pboard );
return( NULL );
}
qmm10xt_reset( pboard );
return( pboard );
}
void GPIO3ModuleClkConfig(void)
{
static char invo_count = 0;
uintptr_t prcm_base;
uint32_t val;
if( invo_count) //第二次调用直接退出
return;
invo_count ++;
prcm_base=mmap_device_io(CM_PRCM_SIZE,PRCM_BASE);
/* Writing to MODULEMODE field of CM_WKUP_GPIO0_CLKCTRL register. */
out32(prcm_base+CM_PER_GPIO3_CLKCTRL,CM_PER_GPIO3_CLKCTRL_MODULEMODE_ENABLE);
/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_PER_GPIO3_CLKCTRL_MODULEMODE_ENABLE !=
(in32(prcm_base + CM_PER_GPIO3_CLKCTRL) &
CM_PER_GPIO3_CLKCTRL_MODULEMODE_ENABLE));
/*
** Writing to OPTFCLKEN_GPIO0_GDBCLK field of CM_WKUP_GPIO0_CLKCTRL
** register.
*/
val=in32(prcm_base + CM_PER_GPIO3_CLKCTRL);
val|=CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK;
out32(prcm_base + CM_PER_GPIO3_CLKCTRL,val);
/* Waiting for OPTFCLKEN_GPIO0_GDBCLK field to reflect the written value. */
while(CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK !=
(in32( prcm_base + CM_PER_GPIO3_CLKCTRL) &
CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK));
}
int main (int argc, char *argv[])
{
int opt = 0, verbose = 0, pin = -1, direction = -1, gpio_module = -1;
int cmd = -1;
extern char *optarg;
// Handle commandline arguments
// -m gpio_module The GPIO module. Can be a value from 1 to 6
// -p pin The GPIO pin you want to set
// -d direction The direction of the GPIO pin. Can be: 0 (=write)|1(=read)
// -c command Action to perform. Can be: set|reset|read
while ((opt = getopt(argc, argv, "m:p:d:c:v")) != -1) {
switch (opt) {
case 'm':
gpio_module = strtol(optarg, NULL, 10);
if (errno != 0) gpio_module = -1;
break;
case 'p':
pin = strtol(optarg, NULL, 10);
if (errno != 0) pin = -1;
break;
case 'd':
direction = strtol(optarg, NULL, 10);
if (errno != 0 || direction > 1) direction = -1;
if (strcmp(optarg, "write") == 0) direction = 0;
else if (strcmp(optarg, "read") == 0) direction = 1;
else direction = -1;
case 'c':
if (strcmp(optarg, "set") == 0) cmd = 0;
else if (strcmp(optarg, "reset") == 0) cmd = 1;
else if (strcmp(optarg, "read") == 0) cmd = 2;
else cmd = -1;
break;
case 'v':
verbose++;
break;
default:
break;
}
}
if (gpio_module != -1 && pin != -1 && direction != -1 && cmd != -1) {
/* enable this thread to execute i/o functions... */
ThreadCtl(_NTO_TCTL_IO, 0);
//ptr = mmap_device_memory( 0, OMAP35XX_GPIO_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, gpio_base[gpio_module - 1]);
ptr = mmap_device_io(OMAP35XX_GPIO_SIZE, gpio_base[gpio_module - 1]);
ctrl_ptr = mmap_device_io(OMAP35XX_GPIO_SIZE, CONTROL_PADCONF_MMC2_CLK);
if ( (void*)ptr == MAP_FAILED ) {
perror( "mmap_device_memory for physical address failed");
exit( EXIT_FAILURE );
}
printf("ctrl_ptr %x\n",in32(ctrl_ptr));
//out32(ctrl_ptr, 0x01040000);
gpio_set_direction(pin, direction);
if (cmd == 0) gpio_set(pin);
if (cmd == 1) gpio_reset(pin);
if (cmd == 2) printf("0x%x\n",gpio_read(direction, pin));
//munmap_device_memory(gpio_base[gpio_module - 1], OMAP35XX_GPIO_SIZE);
munmap_device_io(gpio_base[gpio_module - 1], OMAP35XX_GPIO_SIZE);
munmap_device_io(CONTROL_PADCONF_MMC2_CLK, OMAP35XX_GPIO_SIZE);
return 0;
} else {
printf("Illigal commandline options provided, type 'use %s' on the commandline for usage information:\n", argv[0]);
return -1;
}
}
//#define CM_PER_GPIO1_CLKCTRL (0xAC) // This register manages the GPIO1 clocks. Section 8.1.2.1.41
//#define CM_PER_GPIO2_CLKCTRL (0xB0) // This register manages the GPIO2 clocks. Section 8.1.2.1.42
//#define CM_PER_GPIO3_CLKCTRL (0xB4) // This register manages the GPIO3 clocks. Section 8.1.2.1.43
//#define CM_PER_GPIO4_CLKCTRL (0xB8) // This register manages the GPIO4 clocks. Section 8.1.2.1.44
void GPIO0ModuleClkConfig(void)
{
static char invo_count = 0;
uintptr_t prcm_base,cm_wkup_regs;
uint32_t val;
if( invo_count) //第二次调用直接退出
return;
invo_count ++;
prcm_base=mmap_device_io(CM_PRCM_SIZE,PRCM_BASE);
cm_wkup_regs=prcm_base+0x400;
/* Writing to MODULEMODE field of CM_WKUP_GPIO0_CLKCTRL register. */
out32(cm_wkup_regs+CM_WKUP_GPIO0_CLKCTRL,CM_WKUP_GPIO0_CLKCTRL_MODULEMODE_ENABLE);
/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_WKUP_GPIO0_CLKCTRL_MODULEMODE_ENABLE !=
(in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
CM_WKUP_GPIO0_CLKCTRL_MODULEMODE));
/*
** Writing to OPTFCLKEN_GPIO0_GDBCLK field of CM_WKUP_GPIO0_CLKCTRL
** register.
*/
val=in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL);
val|=CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK;
out32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL,val);
/* Waiting for OPTFCLKEN_GPIO0_GDBCLK field to reflect the written value. */
while(CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK !=
(in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK));
/* Verifying if the other bits are set to required settings. */
/*
** Waiting for IDLEST field in CM_WKUP_CONTROL_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT) !=
(in32(cm_wkup_regs + CM_WKUP_CONTROL_CLKCTRL) &
CM_WKUP_CONTROL_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_L3_AON_GCLK field in CM_L3_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK !=
(in32(cm_wkup_regs + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK));
/*
** Waiting for IDLEST field in CM_WKUP_L4WKUP_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_L4WKUP_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_L4WKUP_CLKCTRL_IDLEST_SHIFT) !=
(in32(cm_wkup_regs + CM_WKUP_L4WKUP_CLKCTRL) &
CM_WKUP_L4WKUP_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_L4_WKUP_GCLK field in CM_WKUP_CLKSTCTRL register
** to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK !=
(in32(cm_wkup_regs + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK));
/*
** Waiting for CLKACTIVITY_L4_WKUP_AON_GCLK field in CM_L4_WKUP_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK !=
(in32(cm_wkup_regs + CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL) &
CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK));
/* Writing to IDLEST field in CM_WKUP_GPIO0_CLKCTRL register. */
while((CM_WKUP_GPIO0_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_GPIO0_CLKCTRL_IDLEST_SHIFT) !=
(in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
CM_WKUP_GPIO0_CLKCTRL_IDLEST));
/*
** Waiting for CLKACTIVITY_GPIO0_GDBCLK field in CM_WKUP_GPIO0_CLKCTRL
** register to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_GPIO0_GDBCLK !=
(in32(cm_wkup_regs + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_GPIO0_GDBCLK));
munmap_device_io(prcm_base, CM_PRCM_SIZE);
}
void DisplaySpeed::startThread(){
ctrlDBHandle = mmap_device_io(IO_PORT_SIZE, CTRLDB_ADDRESS);
ctrlDCHandle = mmap_device_io(IO_PORT_SIZE, CTRLDC_ADDRESS);
pthread_create(&dsio, NULL, &calculationStateDisplayHelper, this);
}
int main(int argc, char *argv[]) {
uint32_t l;
int id, id2;
my_data_t msg;
int rcvid;
name_attach_t *name;
printf("Welcome Onda\n");
if (ThreadCtl(_NTO_TCTL_IO, 0) < 0) {
perror(NULL);
return -1;
}
name = name_attach(NULL, "onda", NAME_FLAG_ATTACH_GLOBAL);
if (name == NULL) {
perror("Error0\n");
return -1;
}
/* attach GPIO interrupt */
id = InterruptAttach (33, gpio_isr_handler, NULL, 0, _NTO_INTR_FLAGS_PROCESS);
/* attach timer interrupt */
id2 = InterruptAttach (45, timer_isr_handler, NULL, 0, _NTO_INTR_FLAGS_PROCESS);
gpio5 = mmap_device_io(OMAP3530_GPIO_SIZE, OMAP3530_GPIO5_BASE);
if (gpio5 == MAP_DEVICE_FAILED) {
perror(NULL);
return -1;
}
//gpt3 = mmap_device_io(OMAP3530_GPT_SIZE, OMAP3530_GPT3_BASE);
gpt9 = mmap_device_io(OMAP3530_GPT_SIZE, OMAP3530_GPT9_BASE);
if (gpt9 == MAP_DEVICE_FAILED) {
perror(NULL);
return -1;
}
sys = mmap_device_io(OMAP3530_SYSCTL_SIZE, OMAP3530_SYSCTL_BASE);
if (sys == MAP_DEVICE_FAILED) {
perror(NULL);
return -1;
}
/* selecting mode 4 function - GPIO 139
* selecting pullup and mode 4 function - GPIO 138 */
#define SYS_CONF ((4 << 16) | ((1 << 8) | (1<<3) | 4))
#define SYS_MASK ~(0x10F010F)
l = (in32(sys + 0x168) & SYS_MASK) | SYS_CONF;
//l = (in32(sys + 0x168) & ~(7<<16) ) | (4 << 16);
//out32(sys + 0x168, ((1<<3 | 4) << 16) | (1<<3) | 4);
out32(sys + 0x168, l);
/* setting mode 2 - PWM */
l = (in32(sys + 0x174) & ~7 ) | 2;
out32(sys + 0x174, l);
/* setting the PIN 138 to input
* setting the PIN 139 to output */
l = (in32(gpio5 + OMAP2420_GPIO_OE) & ~(1 << 11)) | 1 << 10;
out32(gpio5 + OMAP2420_GPIO_OE, l);
/* enabling interrupt on both levels on GPIO 139 */
out32(gpio5 + OMAP2420_GPIO_RISINGDETECT, l << 10);
out32(gpio5 + OMAP2420_GPIO_FALLINGDETECT, l << 10);
out32(gpio5 + OMAP2420_GPIO_SETIRQENABLE1, l << 10);
/* make sure timer has stop */
out32(gpt9 + OMAP3530_GPT_TCLR, 0);
/* enabling the interrupt */
out32(gpt9 + OMAP3530_GPT_TIER, 2); //comentar se PWM
/* configuring PWM */
out32(gpt9 + OMAP3530_GPT_TCLR, (1<<12) | (1<<10) | (1<<7)); //-- PWM
out32(gpio5 + OMAP2420_GPIO_SETDATAOUT, (1 << 11));
printf("Esperando requisições\n");
while (1) {
rcvid = MsgReceive(name->chid, &msg, sizeof(msg), NULL);
if (rcvid == -1) {/* Error condition, exit */
break;
}
/* name_open() sends a connect message, must EOK this */
if (msg.hdr.type == _IO_CONNECT) {
MsgReply(rcvid, EOK, NULL, 0);
continue;
}
/* Some other QNX IO message was received; reject it */
if (msg.hdr.type > _IO_BASE && msg.hdr.type <= _IO_MAX) {
MsgError(rcvid, ENOSYS);
continue;
}
switch (msg.hdr.subtype) {
case 0x55:
MsgReply(rcvid, EOK, &pincount, sizeof(pincount));
break;
case 0x65:
MsgReply(rcvid, EOK, &interval, sizeof(interval));
break;
case 0x66:
interval = msg.data;
MsgReply(rcvid, EOK, &interval, sizeof(interval));
break;
default:
MsgReply(rcvid, EOK, NULL, 0);
}
}
out32(gpt9 + OMAP3530_GPT_TCLR, 0);
out32(gpt9 + OMAP3530_GPT_TIER, 0);
InterruptDetach (id);
InterruptDetach (id2);
printf("Fim\n");
return EXIT_SUCCESS;
}
void *omap3_init(void *hdl, char *options)
{
omap3_spi_t *dev;
uintptr_t base;
int i;
uint32_t reg;
dev = calloc(1, sizeof(omap3_spi_t));
if (dev == NULL)
return NULL;
//Set defaults
dev->pbase = OMAP3_SPI1_BASE;
dev->irq_spi = OMAP3_SPI_SPI1_INTR;
dev->clock = OMAP3_SPI_INPUT_CLOCK;
dev->channel_num = 1;
dev->force = 0;
dev->edmapbase = DM816x_EDMA_BASE;
dev->irq_edma = 0; /* We use interrupt of receive channel */
dev->edma = 0;
dev->num_cs = 1;
dev->cs_delay = 0;
dev->edma_tx_chid = dev->edma_rx_chid = -1;
if (omap3_options(dev, options))
goto fail0;
/*
* Map in SPI registers
*/
if ((base = mmap_device_io(OMAP3_SPI_REGLEN, dev->pbase)) == (uintptr_t)MAP_FAILED)
goto fail0;
dev->vbase = base;
/* Reset the SPI interface
* and wait for the reset to complete
*/
set_port(base + OMAP3_MCSPI_SYS_CONFIG, OMAP3_MCSPI_CONFIG_SOFT_RESET, OMAP3_MCSPI_CONFIG_SOFT_RESET);
while ( !(in32(base + OMAP3_MCSPI_SYS_CONFIG) & 1)) {
nanospin_ns(20);
}
/*Set Master mode -- single channel mode*/
out32((base + OMAP3_MCSPI_MODCTRL_OFFSET), (in32(base + OMAP3_MCSPI_MODCTRL_OFFSET) & OMAP3_MCSPI_MODCTRL_MASTER_SEL)|OMAP3_MCSPI_MODCTRL_MULTI_CH_SEL);
/*
* Calculate all device configuration here
*/
for (i = 0; i < dev->num_cs; i++){ //we have just one device defined in the driver till now....
devctrl[i] = omap3_cfg(dev, &devlist[i].cfg);
if(dev->force){
/* if we need to set the default CSx level to other than defaul low, we need to kick it*/
out32((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14 * i), devctrl[i]|SPI_COMM_TX_RX <<12);
set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, OMAP3_MCSPI_CHANNEL_ENABLE);
/* force CS */
set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, OMAP3_MCSPI_FORCE_MODE_ONE);
delay(1);
/*un force CS */
set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, 0);
set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, 0);
}
}
/*
* Attach SPI interrupt
*/
if (omap3_attach_intr(dev))
goto fail1;
dev->spi.hdl = hdl;
/* Clear the appropriate Interrupts if any*/
reg= in32(base + OMAP3_MCSPI_IRQ_STATUS_OFFSET) ;
out32((base + OMAP3_MCSPI_IRQ_STATUS_OFFSET), reg);
if (dev->edma) {
if (omap3_init_edma(dev)) dev->edma=0;
/*
* Attach SDMA interrupt
*/
if (omap3_edma_attach_intr(dev)){
printf("%s(%d): omap3_edma_attach_intr failed\n", __func__, __LINE__);
goto fail2;
}
}
return dev;
fail2:
munmap_device_memory ((void *)dev->edmavbase, DM6446_EDMA_SIZE);
fail1:
munmap_device_io(dev->vbase, OMAP3_SPI_REGLEN);
fail0:
free(dev);
return NULL;
}
int hsmci_init (SIM_HBA *hba)
{
CONFIG_INFO *cfg;
SIM_MMC_EXT *ext;
hsmci_ext_t *hsmci = NULL;
uintptr_t base;
ext = (SIM_MMC_EXT *)hba->ext;
cfg = (CONFIG_INFO *)&hba->cfg;
hba->verbosity = 4;
if (!ext->opts) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: missing board-specific options\n");
goto ARGSERR;
}
if ((hsmci = calloc(1, sizeof(hsmci_ext_t))) == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: alloc memory failed\n");
goto ERR;
}
cfg->MemLength[0] = 0x1000;
cfg->NumMemWindows = 1;
cfg->MemBase[0] = cfg->IOPort_Base[0];
base = (uintptr_t)mmap_device_memory(NULL, cfg->MemLength[0],
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, cfg->MemBase[0]);
if (base == (uintptr_t)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
hsmci->clock = 133000000;
hsmci->base = base;
hsmci->hba = hba;
ext->handle = hsmci;
ext->clock = hsmci->clock;
ext->detect = _hsmci_detect;
ext->powerup = _hsmci_powerup;
ext->powerdown = _hsmci_powerdown;
ext->cfg_bus = _hsmci_cfg_bus;
ext->set_clock = _hsmci_clock;
ext->set_blksz = _hsmci_block_size;
ext->interrupt = _hsmci_interrupt;
ext->command = _hsmci_command;
ext->setup_dma = _hsmci_setup_dma;
ext->dma_done = _hsmci_dma_done;
ext->setup_pio = _hsmci_setup_pio;
ext->pio_done = _hsmci_pio_done;
ext->shutdown = _hsmci_shutdown;
/* Parse options */
hsmci->port = -1;
hsmci->blksz = BLK_LENGTH;
hsmci->slot = 0;
/* Hardcode DMAC controller base address according to G45 datasheet
* since this driver is specifically for G45 SoC */
hsmci->dbase = DMAC_BASE;
if (!ext->opts)
goto ARGSERR;
if (hsmci_args(hba, ext->opts) == -1)
goto ARGSERR;
/*
* Set Src/Dst Request peripheral identifier SRC_PER/DST_PER
* handshaking interface # according to Table 41-1 DMA Channel Definition
* According to datasheet Table 35-2, the I/O line of mci0_da0 is pa2.
* According to datasheet Table 35-2, the I/O line of mci1_da0 is pa23.
*/
if (hsmci->port == 0) {
hsmci->dintf = 0;
hsmci->da0_mask = (1<<2);
} else {
hsmci->dintf=13;
hsmci->da0_mask = (1<<23);
}
/* Map G45 PIOA for polling busy signal */
pioa_pdsr = (uint32_t *)mmap_device_memory(NULL, 4,
PROT_READ | PROT_WRITE | PROT_NOCACHE, MAP_SHARED, PIOA_PDSR);
if (pioa_pdsr == (uint32_t *)MAP_FAILED) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_memory failed\n");
goto ERR;
}
if ( (uintptr_t) MAP_FAILED == ( hsmci->pio_base = mmap_device_io( AT91SAM9G45_PIO_SIZE, AT91SAM9G45_PIOD_BASE ) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PIOD_PDSR failed" );
goto ERR;
}
/* Configure CD and WP PIO */
InterruptDisable();
#define CFG_PIO(reg) out32( hsmci->pio_base + (reg), AT91SAM9G45_MCI_PIO_BITS )
CFG_PIO( AT91SAM9G45_PIO_PER ); /* Ensable PIO */
CFG_PIO( AT91SAM9G45_PIO_ODR ); /* Disable output */
CFG_PIO( AT91SAM9G45_PIO_IFDR ); /* Disable glitch input filter */
CFG_PIO( AT91SAM9G45_PIO_CODR ); /* Clear output data */
CFG_PIO( AT91SAM9G45_PIO_IDR ); /* Disable interrupt */
CFG_PIO( AT91SAM9G45_PIO_MDDR ); /* Disable multi-driver */
CFG_PIO( AT91SAM9G45_PIO_PUER ); /* Enable pull-up */
CFG_PIO( AT91SAM9G45_PIO_OWDR ); /* Output write disable */
#undef CFG_PIO
InterruptEnable();
/* Configure capacity of controller */
ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS;
// Use the flag MMC_HCCAP_NOCD_BUSY to inform the MMCSD stack that this hardware has R1B bug
// ext->hccap |= MMC_HCCAP_BW1 | MMC_HCCAP_BW4 | MMC_HCCAP_DMA | MMC_HCCAP_BW8 | MMC_HCCAP_HS | MMC_HCCAP_NOCD_BUSY;
/* Disable the controller and soft reset */
WRITE32(MCI_CR, SWRST | PWSDIS);
delay (100);
WRITE32(MCI_CR, MCIDIS | PWSDIS);
/* Disable DMA */
WRITE32(MCI_DMA, (READ32(MCI_DMA) & (~(DMAEN))));
/* Enable the controller */
WRITE32(MCI_CR, MCIEN | PWSDIS);
WRITE32(MCI_IDR, 0xffffffff);
/* Set Timeout to Max */
WRITE32(MCI_DTOR, 0x7f);
/* Use the lowest baudrate */
WRITE32 (MCI_MR, 0xff | WRPROOF| RDPROOF);
hsmci->dmac_dev = dmac_init(hsmci);
if (hsmci->dmac_dev == NULL) {
slogf (_SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: dmafuncs init FAILED\n");
goto ERR;
}
hsmci->dmac_dev->io_addr = cfg->MemBase[0] + MCI_FIFO;
hsmci->dmac_dev->blksz = hsmci->blksz;
/* Select slot, set bus to 1 bit */
WRITE32 (MCI_SDCR, hsmci->slot);
if (!cfg->Description[0])
strncpy(cfg->Description, "Atmel HSMCI ", sizeof(cfg->Description));
if ( (uintptr_t) MAP_FAILED == ( hsmci->pmc_base = mmap_device_io(PMC_SIZE, PMC_BASE) ) ) {
slogf( _SLOGC_SIM_MMC, _SLOG_ERROR, "MMC: mmap_device_io for PMC failed" );
goto ERR;
}
return (MMC_SUCCESS);
ARGSERR:
printf("\nImproper board-specific options used. Accepting args: \n");
printf(" port=# The MCI port been used (0 or 1)\n");
printf("NOTE:\n");
printf(" 1. The args are seperated by colon ':'\n");
printf("Example:\n");
printf("at91sam9g45 port 0: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFF80000,irq=11,bs=port=0\n");
printf("at91sam9g45 port 1: devb-mmcsd-at91sam9g45 mmcsd ioport=0xFFFD0000,irq=29,bs=port=1\n");
ERR:
if (hsmci) {
munmap_device_memory ((void *)hsmci->base, (uint32_t)cfg->MemLength[0]);
if (hsmci->pio_base)
munmap_device_io (hsmci->pio_base, AT91SAM9G45_PIO_SIZE);
free (hsmci);
}
if (pioa_pdsr != (uint32_t *)MAP_FAILED)
munmap_device_memory ((void *)pioa_pdsr, 4);
return (MMC_FAILURE);
}
DEV_OMAP *
create_device(TTYINIT_OMAP *dip, unsigned unit, unsigned maxim_xcvr_kick) {
DEV_OMAP *dev;
unsigned i;
uintptr_t port;
unsigned char msr;
unsigned char tlr = 0, tcr = 0;
#ifdef PWR_MAN
clk_enable_t clk_cfg = clk_enable_none;
#endif
// Get a device entry and the input/output buffers for it.
if ((dev = malloc(sizeof(*dev))) == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of device entry failed (%d)", errno);
return (dev);
}
memset(dev, 0, sizeof(*dev));
// Get buffers.
dev->tty.ibuf.head = dev->tty.ibuf.tail = dev->tty.ibuf.buff = malloc(dev->tty.ibuf.size = dip->tty.isize);
if (dev->tty.ibuf.buff == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of input buffer failed (%d)", errno);
free(dev);
return (NULL);
}
dev->tty.obuf.head = dev->tty.obuf.tail = dev->tty.obuf.buff = malloc(dev->tty.obuf.size = dip->tty.osize);
if (dev->tty.obuf.buff == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of output buffer failed (%d)", errno);
free(dev->tty.ibuf.buff);
free(dev);
return (NULL);
}
dev->tty.cbuf.head = dev->tty.cbuf.tail = dev->tty.cbuf.buff = malloc(dev->tty.cbuf.size = dip->tty.csize);
if (dev->tty.cbuf.buff == NULL)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Allocation of canonical buffer failed (%d)", errno);
free(dev->tty.ibuf.buff);
free(dev->tty.obuf.buff);
free(dev);
return (NULL);
}
if (dip->tty.highwater)
dev->tty.highwater = dip->tty.highwater;
else
dev->tty.highwater = dev->tty.ibuf.size - (FIFO_SIZE * 2);
strcpy(dev->tty.name, dip->tty.name);
dev->tty.baud = dip->tty.baud;
dev->tty.fifo = dip->tty.fifo;
dev->tty.verbose = dip->tty.verbose;
port = mmap_device_io(OMAP_UART_SIZE, dip->tty.port);
for (i = 0; i < OMAP_UART_SIZE; i += 4)
dev->port[i] = port + i;
dev->intr = dip->tty.intr;
dev->clk = dip->tty.clk;
dev->div = dip->tty.div;
dev->tty.flags = EDIT_INSERT | LOSES_TX_INTR;
dev->tty.c_cflag = dip->tty.c_cflag;
dev->tty.c_iflag = dip->tty.c_iflag;
dev->tty.c_lflag = dip->tty.c_lflag;
dev->tty.c_oflag = dip->tty.c_oflag;
dev->tty.lflags = dip->tty.lflags;
if (dip->tty.logging_path[0] != NULL)
dev->tty.logging_path = strdup(dip->tty.logging_path);
#ifdef PWR_MAN
dev->physbase = dip->tty.port;
if (omap_clock_toggle_init(dev) != EOK)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Fail to initialize clocks for PM!");
free(dev->tty.ibuf.buff);
free(dev->tty.obuf.buff);
free(dev);
return (NULL);
}
#ifdef WINBT
clk_cfg = clk_enable_smart_wkup;
if (omap_force_rts_init(dev) != EOK)
{
slogf(_SLOG_SETCODE(_SLOGC_CHAR, 0), _SLOG_ERROR, "io-char: Fail to initialize force_rts for PM!");
free(dev->tty.ibuf.buff);
free(dev->tty.obuf.buff);
free(dev);
return (NULL);
}
#endif
omap_clock_enable(dev, clk_cfg);
#ifdef WINBT
bt_ctrl_init();
#endif
#endif
/* Set auto_rts mode */
dev->auto_rts_enable = dip->auto_rts_enable;
// Do not enable MSR interrupt
dev->no_msr_int = dip->no_msr_int;
// Initialize termios cc codes to an ANSI terminal.
ttc(TTC_INIT_CC, &dev->tty, 0);
// Initialize the device's name.
// Assume that the basename is set in device name. This will attach
// to the path assigned by the unit number/minor number combination
unit = SET_NAME_NUMBER(unit) | NUMBER_DEV_FROM_USER;
ttc(TTC_INIT_TTYNAME, &dev->tty, unit);
// see if we have a maxim rs-232 transceiver that needs to be
// kicked after it goes to sleep
dev->kick_maxim = maxim_xcvr_kick;
// Only setup IRQ handler for non-pcmcia devices.
// Pcmcia devices will have this done later when card is inserted.
if (dip->tty.port != 0 && dip->tty.intr != _NTO_INTR_SPARE) {
#ifdef OMAP5910
/*
* Don't change default mode set in the very distant past. Even though
* MODE_SELECT should be DISABLE before changing DLH, DLL.
*/
// enable the UART
write_omap(dev->port[OMAP_UART_MDR1], OMAP_MDR1_MODE_16X);
#else
/*
* TRM states: Before initializing or modifying clock parameter controls
* (DLH, DLL), MODE_SELECT must be set to 0x7 (DISABLE). Failure to observe
* this rule can result in unpredictable module behavior.
*/
write_omap(dev->port[OMAP_UART_MDR1], OMAP_MDR1_MODE_DISABLE);
#endif
/* Work around for silicon errata i202 states: */
/* Need a delay = 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) */
nanospin_ns(200);
/* Clear FIFOs */
set_port(dev->port[OMAP_UART_FCR], OMAP_FCR_RXCLR | OMAP_FCR_TXCLR, OMAP_FCR_RXCLR | OMAP_FCR_TXCLR);
/* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and TX_FIFO_E bit is 1 */
i = 5;
while ((read_omap(dev->port[OMAP_UART_LSR]) & (OMAP_UART_LSR_THRE | OMAP_UART_LSR_DR)) != OMAP_UART_LSR_THRE)
{
nanospin_ns(200);
if (--i == 0)
{
break; /* No need to do anything drastic if FIFO is still not empty */
}
}
// enable access to divisor registers
write_omap(dev->port[OMAP_UART_LCR], OMAP_LCR_DLAB);
write_omap(dev->port[OMAP_UART_DLL], 0);
write_omap(dev->port[OMAP_UART_DLH], 0);
/* Switch to config mode B to get access to EFR Register */
write_omap(dev->port[OMAP_UART_LCR], 0xBF);
/* Enable access to TLR register */
set_port(dev->port[OMAP_UART_EFR], OMAP_EFR_ENHANCED, OMAP_EFR_ENHANCED);
/* Switch to operational mode to get acces to MCR register */
write_omap(dev->port[OMAP_UART_LCR], 0x00);
/* set MCR bit 6 to enable access to TCR and TLR registers */
set_port(dev->port[OMAP_UART_MCR], OMAP_MCR_TCRTLR, OMAP_MCR_TCRTLR);
write_omap(dev->port[OMAP_UART_FCR], OMAP_FCR_ENABLE|OMAP_FCR_RXCLR|OMAP_FCR_TXCLR);
tcr = 0x0e; /* set auto-rts assert at 56 bytes, restore at 0 bytes */
if (dev->tty.fifo)
{
/* Set RX fifo trigger level */
switch (dev->tty.fifo >> 4) {
case FIFO_TRIG_8:
default:
tlr = 0x20;
break;
case FIFO_TRIG_16: tlr = 0x40; break;
case FIFO_TRIG_32: tlr = 0x80; break;
case FIFO_TRIG_56: tlr = 0xe0; break;
case FIFO_TRIG_60:
tlr = 0xf0;
tcr = 0x0f; /* Ensure auto-rts trigger is not less the RX trigger */
break;
}
/* Set TX fifo trigger level */
switch (dev->tty.fifo & 0x0f) {
case FIFO_TRIG_8:
default:
tlr |= 0x02;
break;
case FIFO_TRIG_16: tlr |= 0x04; break;
case FIFO_TRIG_32: tlr |= 0x08; break;
case FIFO_TRIG_56: tlr |= 0x0e; break;
case FIFO_TRIG_60: tlr |= 0x0f; break;
}
}
write_omap(dev->port[OMAP_UART_TCR], tcr);
write_omap(dev->port[OMAP_UART_TLR], tlr);
#ifdef PWR_MAN
write_omap(dev->port[OMAP_UART_SCR], OMAP_SCR_WAKEUPEN);
#else
write_omap(dev->port[OMAP_UART_SCR], 0x00);
#endif
/* Switch back to Config mode B to gain access to EFR again */
write_omap(dev->port[OMAP_UART_LCR], 0xBF);
/* remove access to TLR register */
set_port(dev->port[OMAP_UART_EFR], OMAP_EFR_ENHANCED, 0);
/* Switch to operational mode to get acces to MCR register */
write_omap(dev->port[OMAP_UART_LCR], 0x00);
/* clr MCR bit 6 to remove access to TCR and TLR registers */
set_port(dev->port[OMAP_UART_MCR], OMAP_MCR_TCRTLR, 0);
ser_stty(dev);
ser_attach_intr(dev);
}
/*
* Control.cpp
*
* Created on: Mar 12, 2015
* Author: ajm5774
*/
#include "Control.h"
#include <stdio.h>
#include <stdint.h>
#include <sys/mman.h>
uintptr_t Control::ctrlHandle = mmap_device_io(PORT_LENGTH, DAQ_CTRL);
uintptr_t Control::inputHandle = mmap_device_io(PORT_LENGTH,DAQ_INPUT);
uintptr_t Control::outputAHandle = mmap_device_io(PORT_LENGTH,DAQ_OUTPUTA);
uintptr_t Control::outputBHandle = mmap_device_io(PORT_LENGTH,DAQ_OUTPUTB);
uint8_t Control::OUTPUTA = 0x00;
uint8_t Control::OUTPUTB = 0x00;
Control::Control(){
printf("Control made\n");
}
Control::Control(StateContext * aContext)
{
context = aContext;
}
void Control::run()
{
static err_t gpio_init(Drive_Gpio *t)
{
Drive_Gpio *cthis = ( Drive_Gpio *)t ;
uint32_t tmp_reg = 0;
gpio_cfg *config = cthis->config;
int i = 0;
assert( config->intr_line < 2);
cthis->gpio_vbase = mmap_device_io( AM335X_GPIO_SIZE, GpioBase[ config->pin_group]);
#ifdef DEBUG_GPIO
TRACE_INFO("Drive Piling :%s-%s-%d \r\n", __FILE__, __func__, __LINE__);
TRACE_INFO("pin config 0x%04x \r\n", rd_pin_conf( config->pin_ctrl_off));
return EXIT_SUCCESS;
#else
if (cthis->gpio_vbase == MAP_DEVICE_FAILED)
{
return ERROR_T( gpio_init_mapio_fail);
}
gpioModuleConfig[ config->pin_group]();
GPIOModuleEnable( cthis->gpio_vbase);
//配置引脚方向为输入
tmp_reg = in32( cthis->gpio_vbase + GPIO_OE );
tmp_reg |= 1 << config->pin_number;
out32( cthis->gpio_vbase + GPIO_OE, tmp_reg );
//使能消抖
tmp_reg=in32( cthis->gpio_vbase + GPIO_DEBOUNCENABLE);
tmp_reg &=~( 1 << config->pin_number);
tmp_reg |= ( 1 << config->pin_number);
out32( cthis->gpio_vbase + GPIO_DEBOUNCENABLE, tmp_reg);
//消抖时间
out32( cthis->gpio_vbase + GPIO_DEBOUNCINGTIME, ( config->debou_time ));
//配置中断监测类型
for( i = 0; i < 4; i ++)
{
if( ( ( 1 << i) & config->intr_type) )
{
//使能该类型
tmp_reg = in32( cthis->gpio_vbase + GPIO_DETECT(i));
tmp_reg |= 1 << config->pin_number;
out32(cthis->gpio_vbase + GPIO_DETECT(i), tmp_reg);
}
else
{
//禁止其他类型
tmp_reg = in32( cthis->gpio_vbase + GPIO_DETECT(i));
tmp_reg &= ~(1 << config->pin_number);
out32(cthis->gpio_vbase + GPIO_DETECT(i), tmp_reg);
}
}
//使能引脚中断
// tmp_reg = in32( cthis->gpio_vbase + GPIO_IRQSTATUS_SET( config->intr_line));
// tmp_reg |= 1 << config->pin_number;
// out32(cthis->gpio_vbase + GPIO_IRQSTATUS_SET( config->intr_line), tmp_reg);
#ifdef DEBUG_GPIO
dump_gpio_reg( cthis->gpio_vbase);
#endif
SIGEV_INTR_INIT( &cthis->isr_event );
cthis->irq_id = InterruptAttach_r ( GpioIntNum[ config->intr_line][ config->pin_group], gpioExtInteIsr, cthis, 1, _NTO_INTR_FLAGS_END );
return EXIT_SUCCESS;
#endif
}
int _open_PLX9052(int *pci_handle, unsigned int *mmap_io_ptr, int *interrupt_line, int print){
#ifdef __QNX__
volatile unsigned char *BASE0, *BASE1;
unsigned flags, lastbus, version, hardware, bus, device;
int temp;
unsigned pci_index=0;
struct _pci_config_regs pci_reg;
/* CONNECT TO PCI SERVER */
*pci_handle=pci_attach(flags);
if (*pci_handle == -1){
perror("Cannot attach to PCI system");
return -1;
}
/* CHECK FOR PCI BUS */
temp=pci_present(&lastbus, &version, &hardware);
if(temp != PCI_SUCCESS){
perror("Cannot find PCI BIOS");
return -1;
}
/* FIND DEVICE */
temp=pci_find_device(DEVICE_ID, VENDOR_ID, pci_index, &bus, &device);
if(temp != PCI_SUCCESS){
perror("Cannot find GC314-PCI/FS Digital Receiver Card");
return -1;
}
/* READ THE DEVICE PCI CONFIGURATION */
temp=pci_read_config32(bus, device, 0, 16, (char *)&pci_reg);
if(temp != PCI_SUCCESS){
perror("Cannot read from configuration space of the GC314 PCI/FS digital receiver card");
return -1;
}
BASEIO=(int)pci_reg.Base_Address_Regs[1]-1;
/* ALLOW I/O ACCESS ON THIS THREAD */
temp=ThreadCtl(_NTO_TCTL_IO,0);
if (temp==-1){
perror("Unable to attach I/O privileges to thread");
return -1;
}
/* MAP THE IO SPACE TO BE ABLE TO R/W TO PCI IO */
*mmap_io_ptr=(unsigned int *)mmap_device_io(16, pci_reg.Base_Address_Regs[2]);
if ((int)mmap_io_ptr == MAP_DEVICE_FAILED){
perror("Device I/O mapping failed");
return -1;
}
/* TRY TO MEMORY MAP TO THE DEVICE REGISTER SPACE */
//BASE0=mmap_device_memory(0, 256, PROT_EXEC|PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, pci_reg.Base_Address_Regs[0]);
//BASE1=mmap_device_memory(0, 1048576, PROT_EXEC|PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, pci_reg.Base_Address_Regs[2]);
//if ((BASE0 == MAP_FAILED) | (BASE1 == MAP_FAILED)){
// perror("Device Memory mapping failed");
// return -1;
//}
/* TRY TO READ PCI DEVICE PARAMETERS */
//pci_write_config16(bus, device, PLX9656_PCIICR, 1, &vPLX9656_PCIICR);
//*((uint16*)(BASE0+PLX9656_BIGEND))=vPLX9656_BIGEND;
//*((uint16*)(BASE0+PLX9656_BIGEND))=0;
//*((uint32*)(BASE0+0x4c))=0x48;
//temp=*((uint32*)(BASE0+0x4c));
//printf(" INTCSR is %x\n",temp);
//temp=in32(BASEIO+0x4c);
//printf(" INTCSR is %x\n",temp);
//*BASEA=(int)mmap_io_ptr;
//*BASEB=0;
*interrupt_line=pci_reg.Interrupt_Line;
/* PRINT PLX9656 PARAMETERS */
if (print == 1){
printf(" PCI DEVICE PARAMETERS:\n");
printf(" lastbus= %d\n", lastbus);
printf(" version= %d\n", version);
printf(" hardware= %d\n", hardware);
printf(" bus= %d\n", bus);
printf(" device= %d\n", device);
printf(" MEMORY ALLOCATION:\n");
printf(" IO Base0= 0x%x\n", pci_reg.Base_Address_Regs[0]);
printf(" IO Base1= 0x%x\n", pci_reg.Base_Address_Regs[1]);
printf(" IO Base2= 0x%x\n", pci_reg.Base_Address_Regs[2]);
}
*mmap_io_ptr=pci_reg.Base_Address_Regs[2]-1;
return 1;
#else
return 1;
#endif
}
int main(int argc, char *argv[]) {
int freq;
double setpoint;
uintptr_t ctrlHandle;
char buf[20], file[10];
coefs coefficients;
filter_data data={
{0,0,0},
{0,0,0}
};
// Read initial configuration from the user
printf("log file? (9 chars max)\r\n");
scanf("%s", file);
printf("p:\r\n");
scanf("%lf", &coefficients.p);
printf("i:\r\n");
scanf("%lf", &coefficients.i);
printf("d:\r\n");
scanf("%lf", &coefficients.d);
printf("setpoint:\r\n");
scanf("%lf", &setpoint);
printf("Sample freq?\r\n");
scanf("%d",&freq);
// Open the log file
sprintf(buf,"/tmp/%s.csv",file);
FILE * f = fopen(buf, "w+");
// Increase permissions for access to hardware
if (ThreadCtl(_NTO_TCTL_IO, NULL) == -1){
perror("Failed to get I/O access permission");
return 1;
}
// Get a handle to write to hardware ATD and DAC
ctrlHandle = mmap_device_io(IO_PORT_SIZE, CTRL_ADDRESS);
if (ctrlHandle == MAP_DEVICE_FAILED) {
perror("Failed to map control register");
return 2;
}
// Create and initialize semaphores
sem_t filter_sem, DAC_sem, write_lock;
sem_init(&filter_sem,0,0);
sem_init(&DAC_sem,0,0);
sem_init(&write_lock,0,0);
//set up args for our threads
adc_args adcargs = {
ctrlHandle, // uintptr_t handle
&data, // filter_data * data
&filter_sem, // sem_t * filter_sem
&DAC_sem, // sem_t * DAC_sem
&setpoint, // double * setpoint
f // FILE * f
};
filter_args filtargs = {
&data, // filter_data * data
&coefficients, // coefs * coefficients
&filter_sem, // sem_t * filter_sem
&write_lock, // sem_t * write_lock
&DAC_sem, // sem_t * DAC_sem
f // FILE * f
};
dac_args dacargs = {
&data, // filter_data * data
ctrlHandle, // uintptr_t handle
&DAC_sem, // sem_t DAC_sem
f // FILE * f
};
input_thread_args inputargs = {
&write_lock, // sem_t * write_lock
&coefficients, // coefs * coefficient_struct
&setpoint // double * setpoint
};
// Initialize hardware
init_da(ctrlHandle);
// Start the system
scheduleATD(1000000000/freq,ctrlHandle,&adcargs);
pthread_t filter_pthread, DAC_pthread, input_pthread;
pthread_create(&filter_pthread,NULL,&filter_thread,(void*)&filtargs);
pthread_create(&DAC_pthread,NULL,&DAC_thread,(void*)&dacargs);
pthread_create(&input_pthread,NULL, &start_input_thread, (void*)&inputargs);
// Wait for the threads to finish (won't happen, run forever)
pthread_join(filter_pthread,NULL);
pthread_join(DAC_pthread,NULL);
pthread_join(input_pthread,NULL);
return EXIT_SUCCESS;
}
