/**
* \brief Disable the clock to peripheral \a id on port \a port
*
* \param port ID of the port to which the module is connected (one of
* the SYSCLK_PORT_* definitions).
* \param id The ID (bitmask) of the peripheral module to be disabled
*/
void sysclk_disable_module(uint8_t port, uint8_t id)
{
irqflags_t iflags;
uint8_t mask;
iflags = cpu_irq_save();
mask = mmio_read8((void *)(PR_BASE + port));
mask |= id;
mmio_write8((void *)(PR_BASE + port), mask);
cpu_irq_restore(iflags);
}
static void uart_pl011_init(struct uart_chip *chip)
{
if (chip->divider) {
mmio_write16(chip->base + UARTCR, 0);
while (mmio_read8(chip->base + UARTFR) & UARTFR_BUSY)
cpu_relax();
mmio_write16(chip->base + UARTIBRD, chip->divider);
mmio_write8(chip->base + UARTLCR_H, UARTLCR_H_WLEN);
mmio_write16(chip->base + UARTCR, UARTCR_EN | UARTCR_TXE |
UARTCR_Out1 | UARTCR_Out2);
}
}
/**
* Read from PCI config space.
* @param bdf 16-bit bus/device/function ID of target.
* @param address Config space access address.
* @param size Access size (1, 2 or 4 bytes).
*
* @return Read value.
*
* @see pci_write_config
*/
u32 pci_read_config(u16 bdf, u16 address, unsigned int size)
{
void *mmcfg_addr = pci_get_device_mmcfg_base(bdf) + address;
if (!pci_space || PCI_BUS(bdf) > end_bus)
return arch_pci_read_config(bdf, address, size);
if (size == 1)
return mmio_read8(mmcfg_addr);
else if (size == 2)
return mmio_read16(mmcfg_addr);
else
return mmio_read32(mmcfg_addr);
}
static int lua_mmio_read8(lua_State *L) {
mmio_t *mmio;
uint8_t value;
uintptr_t offset;
int ret;
mmio = luaL_checkudata(L, 1, "periphery.MMIO");
lua_mmio_checktype(L, 2, LUA_TNUMBER);
offset = lua_tounsigned(L, 2);
if ((ret = mmio_read8(mmio, offset, &value)) < 0)
return lua_mmio_error(L, ret, mmio_errno(mmio), "Error: %s", mmio_errmsg(mmio));
lua_pushunsigned(L, value);
return 1;
}
void mmio_perform_access(void *base, struct mmio_access *mmio)
{
void *addr = base + mmio->address;
if (mmio->is_write)
switch (mmio->size) {
case 1:
mmio_write8(addr, mmio->value);
break;
case 2:
mmio_write16(addr, mmio->value);
break;
case 4:
mmio_write32(addr, mmio->value);
break;
#if BITS_PER_LONG == 64
case 8:
mmio_write64(addr, mmio->value);
break;
#endif
}
else
switch (mmio->size) {
case 1:
mmio->value = mmio_read8(addr);
break;
case 2:
mmio->value = mmio_read16(addr);
break;
case 4:
mmio->value = mmio_read32(addr);
break;
#if BITS_PER_LONG == 64
case 8:
mmio->value = mmio_read64(addr);
break;
#endif
}
}
