void __init pxa168_timer_init(void)
{
/* this is early, we have to initialize the CCU registers by
* ourselves instead of using clk_* API. Clock rate is defined
* by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
*/
__raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
/* 3.25MHz, bus/functional clock enabled, release reset */
__raw_writel(TIMER_CLK_RST, APBC_TIMERS);
/*
* Make use of timer 1 which id is 0.
* It has no shadow and crsr regsiters.
* The fast lock is 3.25M.
* apb bus is 26M.
*/
mmp_timer_init(0, TIMERS1_VIRT_BASE, 0, 3250000, 26000000);
/*
* Enable counter 1 to be clock source.
* The frequency is 32K.
*/
mmp_counter_clocksource_init(0, 1, 32768);
/*
* Enable counter 0 to be clock event device.
* The frequency is 32K.
* Only one cpu and there is no broadcast timer.
*/
mmp_counter_clockevent_init(0, 0, IRQ_PXA168_TIMER1, 32768, 0, 0);
}
void __init mmp_dt_init_timer(void)
{
struct device_node *np;
struct clk *clk;
int irq, ret;
unsigned long rate;
np = of_find_matching_node(NULL, mmp_timer_dt_ids);
if (!np) {
ret = -ENODEV;
goto out;
}
clk = of_clk_get(np, 0);
if (!IS_ERR(clk)) {
ret = clk_prepare_enable(clk);
if (ret)
goto out;
rate = clk_get_rate(clk) / 2;
} else if (cpu_is_pj4()) {
rate = 6500000;
} else {
rate = 3250000;
}
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
ret = -EINVAL;
goto out;
}
mmp_timer_base = of_iomap(np, 0);
if (!mmp_timer_base) {
ret = -ENOMEM;
goto out;
}
mmp_timer_init(irq, rate);
return;
out:
pr_err("Failed to get timer from device tree with error:%d\n", ret);
}
