void platform_shutdown()
{
dma_shutdown();
wdt_disable();
arm_disable_caches();
mmu_disable();
}
static bool_t mach_cleanup(void)
{
/* stop timer 0 ~ 4 */
writel(S5PV210_TCON, 0x0);
/* stop system timer */
writel(S5PV210_SYSTIMER_TCON, 0x0);
/* disable irq */
irq_disable();
/* disable fiq */
fiq_disable();
/* disable icache */
icache_disable();
/* disable dcache */
dcache_disable();
/* disable mmu */
mmu_disable();
/* disable vic */
vic_disable();
return TRUE;
}
/*
* Func: post_sysinfo_scan_mmu_setup
* Desc: Once we have scanned coreboot tables, we have complete information
* about different memory ranges. Thus, we can perform a complete mmu
* initialization. Also, this takes care of DMA area setup
*/
static void post_sysinfo_scan_mmu_setup(void)
{
struct memrange *ranges;
uint64_t nranges;
struct mmu_ranges mmu_ranges;
struct mmu_memrange *dma_range;
/* Get memrange info from lib_sysinfo */
lib_sysinfo_get_memranges(&ranges, &nranges);
/* Get memory ranges for mmu init from lib_sysinfo memrange */
dma_range = mmu_init_ranges_from_sysinfo(ranges, nranges, &mmu_ranges);
/* Disable mmu */
mmu_disable();
/* Init mmu */
mmu_init(&mmu_ranges);
/* Enable mmu */
mmu_enable();
/* Init dma memory */
init_dma_memory((void *)dma_range->base, dma_range->size);
}
void init_memory_secondary(){
// Disable MMU
mmu_disable();
// Get the L1 page table base address.
uint32_t * table = (uint32_t *)&__l1_page_table_start;
// write entry table address to TTBR0
_ARM_MCR(15, 0, table, 2, 0, 0);
// set Client mode for all Domains
uint32_t dacr = 0x55555555;
_ARM_MCR(15, 0, dacr, 3, 0, 0); // MCR p15, 0, <Rd>, c3, c0, 0 ; Write DACR
// Enable MMU
mmu_enable();
/****************************************
* Branch prediction
*/
// Disable branch prediction
arm_branch_prediction_disable();
// Invalidate branch prediction array
arm_branch_target_cache_invalidate();
// Branch Prediction Enable
arm_branch_prediction_enable();
/****************************************
* Instruction Cache
*/
// Disable L1 Instruction cache
arm_icache_disable();
// Invalidate Instruction cache
arm_icache_invalidate();
// Enable Instruction cache
arm_icache_enable();
/****************************************
* Data Cache
*/
// Disable L1 Data Caches
arm_dcache_disable();
// Invalidate Data cache
arm_dcache_invalidate();
// Enable Data cache
arm_dcache_enable();
}
void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
{
struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31");
void (*bl31_entry)(bl31_params_t *params, void *plat_params) = NULL;
if (prog_locate(&bl31))
die("BL31 not found");
bl31_entry = selfload(&bl31, false);
if (!bl31_entry)
die("BL31 load failed");
SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0);
if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) {
struct prog bl32 = PROG_INIT(PROG_BL32,
CONFIG_CBFS_PREFIX"/secure_os");
if (prog_locate(&bl32))
die("BL32 not found");
if (cbfs_prog_stage_load(&bl32))
die("BL32 load failed");
SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_1,
PARAM_EP_SECURE);
bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32);
bl32_ep_info.spsr = SPSR_EXCEPTION_MASK |
get_eret_el(EL1, SPSR_USE_L);
bl31_params.bl32_ep_info = &bl32_ep_info;
}
bl31_params.bl33_ep_info = &bl33_ep_info;
SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_1, PARAM_EP_NON_SECURE);
bl33_ep_info.pc = payload_entry;
bl33_ep_info.spsr = payload_spsr;
bl33_ep_info.args.arg0 = payload_arg0;
/* May update bl31_params if necessary. Must flush all added structs. */
void *bl31_plat_params = soc_get_bl31_plat_params(&bl31_params);
dcache_clean_by_mva(&bl31_params, sizeof(bl31_params));
dcache_clean_by_mva(&bl33_ep_info, sizeof(bl33_ep_info));
raw_write_daif(SPSR_EXCEPTION_MASK);
mmu_disable();
bl31_entry(&bl31_params, bl31_plat_params);
die("BL31 returned!");
}
static void execute_elf(void *arg) {
int fd, size, i, j;
void *entry;
//extern void *end;
void *elf_begin = ((void *)(&end)) + 4*1024;
uint8_t *tmp = elf_begin;
printf("Load file to RAM\n");
fd = fat_open(path, O_RDONLY);
size = fat_fsize(fd);
for(j = 512; j < size; j += 512) {
fat_read_sect(fd);
for(i = 0; i < 512; i++) {
*tmp++ = fat_buf[i];
}
}
fat_read_sect(fd);
for(i = 0; i < j - size; i++) {
*tmp++ = fat_buf[i];
}
fat_close(fd);
printf("File loaded\n");
printf("Highest addr used is 0x%X\n", tmp);
//input_poll();
mmu040_init();
terminal_clear();
printf("MMU Init\n");
if(!(entry = elf_load(elf_begin, do_debug))) {
printf("Failed to load ELF\n");
input_poll();
return;
}
printf("ELF load successful, entry is 0x%X, press any key\n", entry);
//input_poll();
//printf("Here we have 0x%X\n", *((uint32_t *) entry));
//input_poll();
mmu_disable();
if(do_debug) {
char *argv[] = {"debug"};
mmu_enable_and_jump(entry, 1, argv);
} else {
mmu_enable_and_jump(entry, 0, NULL);
}
}
/**
* Disable MMU and D-cache, flush caches
* @return 0 (always)
*
* This function is called by shutdown_barebox to get a clean
* memory/cache state.
*/
void arch_shutdown(void)
{
#ifdef CONFIG_MMU
/* nearly the same as below, but this could also disable
* second level cache.
*/
mmu_disable();
#else
asm volatile (
"bl __mmu_cache_flush;"
"bl __mmu_cache_off;"
:
:
: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
);
#endif
}
/*
************************************************************************************************************
*
* function
*
* 函数名称：
*
* 参数列表：
*
* 返回值 ：
*
* 说明 ：
*
*
************************************************************************************************************
*/
void eGon2_jump_to(__u32 addr)
{
eGon2_power_set_data_buffer(0x0e);
eGon2_timer_exit(); //关闭timer
eGon2_key_exit(); //关闭按键
eGon2_twi_exit(); //关闭TWI设备
eGon2_block_device_exit(); //关闭用到的存储设备
close_sys_int( ); // close system interrupt
eGon2_Int_Exit( ); // 关闭所有中断
disable_icache(); // 关闭icache
flush_dcache();
disable_dcache(); // 关闭dcache
mmu_disable(); // 关闭mmu
jump_to( addr );
return;
}
static bool_t mach_cleanup(void)
{
/* disable irq */
irq_disable();
/* disable fiq */
fiq_disable();
/* disable icache */
icache_disable();
/* disable dcache */
dcache_disable();
/* disable mmu */
mmu_disable();
return TRUE;
}
/*
************************************************************************************************************
*
* function
*
* 函数名称：
*
* 参数列表：
*
* 返回值 ：
*
* 说明 ：
*
*
************************************************************************************************************
*/
void eGon2_jump_to_android_linux(__s32 zero, __s32 mod_id, __u32 paddr, __u32 kernal_addr)
{
void (*kernel_entry)(int zero, int arch, uint params);
eGon2_power_set_data_buffer(0x0e);
eGon2_timer_exit(); //关闭timer
eGon2_key_exit(); //关闭按键
eGon2_twi_exit(); //关闭TWI设备
eGon2_block_device_exit(); //关闭用到的存储设备
close_sys_int( ); // close system interrupt
eGon2_Int_Exit( ); // 关闭所有中断
disable_icache(); // 关闭icache
flush_dcache();
disable_dcache(); // 关闭dcache
mmu_disable(); // 关闭mmu
kernel_entry = (void (*)(int, int, __u32))(kernal_addr);
kernel_entry(zero, mod_id, paddr);
return;
}
/*
************************************************************************************************************
*
* function
*
* 函数名称：
*
* 参数列表：
*
* 返回值 ：
*
* 说明 ：
*
*
************************************************************************************************************
*/
void eGon2_simple_jump_Fel( void )
{
eGon2_timer_exit(); //关闭timer
eGon2_key_exit(); //关闭按键
eGon2_twi_exit(); //关闭TWI设备
close_sys_int( ); // close system interrupt
set_vect_high_addr( ); // set interrupt vector low address
eGon2_Int_Exit( ); // 关闭所有中断
disable_icache(); // 关闭icache
flush_dcache();
disable_dcache(); // 关闭dcache
mmu_disable(); // 关闭mmu
{
__u32 timedly;
for(timedly = 0; timedly < 5000; timedly ++);
}
jump_to( FEL_BASE );
return ;
}
void mt8173_mmu_after_dram(void)
{
/* Map DRAM as cached now that it's up and running */
mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
/* Unmap L2C SRAM so it can be reclaimed by L2 cache */
/* TODO: Implement true unmapping, and also use it for the zero-page! */
mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);
mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);
/* Careful: changing cache geometry while it's active is a bad idea! */
mmu_disable();
/* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max
* available L2 cache for A53 in MT8173. */
write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8);
/* turn off the l2c sram clock */
write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN);
/* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
mmu_enable();
}
/*******************************************************************************
*函数名称: Boot0_C_part
*函数原型：void Boot0_C_part( void )
*函数功能: Boot0中用C语言编写的部分的主流程
*入口参数: void
*返 回 值: void
*备 注:
*******************************************************************************/
void Boot0_C_part( void )
{
__u32 status;
__s32 dram_size;
int index = 0;
int ddr_aotu_scan = 0;
volatile unsigned int *reg_addr = 0;
// move_RW( );
clear_ZI( );
bias_calibration();
timer_init();
UART_open( BT0_head.prvt_head.uart_port, (void *)BT0_head.prvt_head.uart_ctrl, 24*1000*1000 );
//odt_status = check_odt(5);
if( BT0_head.prvt_head.enable_jtag )
{
jtag_init( (normal_gpio_cfg *)BT0_head.prvt_head.jtag_gpio );
}
msg("HELLO! BOOT0 is starting!\n");
print_version();
{
__u32 reg_val;
__u32 fel_flag;
fel_flag = *(volatile unsigned int *)(0x01f00000 + 0x108);
//print smp status.
index = 0;
while(index < 0x18)
{
reg_addr = (volatile unsigned int *)(0x01f00000 + 0x100 + index);
reg_val = *reg_addr;
*reg_addr = 0;
msg("reg_addr %x =%x\n", reg_addr, reg_val);
index+=0x4;
}
// reg_val = *(volatile unsigned int *)(0x01f00000 + 0x108);
// *(volatile unsigned int *)(0x01f00000 + 0x108) = 0;
// msg("fel_flag=%x\n", fel_flag);
if(fel_flag == 0x5AA5A55A)
{
msg("eraly jump fel\n");
pll_reset();
__msdelay(10);
jump_to( FEL_BASE );
}
}
mmu_system_init(EGON2_DRAM_BASE, 1 * 1024, EGON2_MMU_BASE);
mmu_enable();
//dram_size = init_DRAM(BT0_head.boot_head.platform[7]); // 初始化DRAM
//#ifdef CONFIG_SUN6I_FPGA
// ddr_aotu_scan = 1;
// msg("config fpga\n");
//#else
// ddr_aotu_scan = BT0_head.boot_head.platform[7];
// msg("not config fpga\n");
//#endif
ddr_aotu_scan = 0;
#ifdef DEBUG
{
int k;
for(k=0;k<16;k++)
{
msg("%x\n", BT0_head.prvt_head.dram_para[k]);
}
}
#endif
// msg("------------before------------\n");
// dram_para_display();
dram_size = init_DRAM(ddr_aotu_scan, (void *)BT0_head.prvt_head.dram_para);
if(dram_size)
{
mdfs_save_value((void *)BT0_head.prvt_head.dram_para);
msg("dram size =%d\n", dram_size);
}
else
{
msg("initializing SDRAM Fail.\n");
mmu_disable( );
pll_reset();
__msdelay(10);
jump_to( FEL_BASE );
}
// {
// __u32 reg_val;
//
// reg_val = *(volatile __u32 *)(0x1c20d20);
// *(volatile __u32 *)(0x1c20d20) = 0;
// msg("reg_val=%x, %x\n", reg_val, *(volatile __u32 *)(0x1c20d24));
// if(reg_val & 0x01)
// {
// mmu_disable( );
// jump_to( 0x40100000 );
// }
// }
// msg("------------end------------\n");
// dram_para_display();
#if SYS_STORAGE_MEDIA_TYPE == SYS_STORAGE_MEDIA_NAND_FLASH
status = load_Boot1_from_nand( ); // 载入Boot1
#elif SYS_STORAGE_MEDIA_TYPE == SYS_STORAGE_MEDIA_SPI_NOR_FLASH
status = load_boot1_from_spinor( ); // 载入Boot1
#elif SYS_STORAGE_MEDIA_TYPE == SYS_STORAGE_MEDIA_SD_CARD
status = load_boot1_from_sdmmc( (char *)BT0_head.prvt_head.storage_data ); // 载入boot1
#else
#error The storage media of Boot1 has not been defined.
#endif
msg("Ready to disable icache.\n");
mmu_disable( ); // disable instruction cache
if( status == OK )
{
// restart_watch_dog( ); // restart watch dog
//跳转boot1之前，把dram的大小写进去
//set_dram_size(dram_size );
//跳转之前，把所有的dram参数写到boot1中
set_dram_para((void *)&BT0_head.prvt_head.dram_para, dram_size);
msg("Succeed in loading Boot1.\n"
"Jump to Boot1.\n");
jump_to( BOOT1_BASE ); // 如果载入Boot1成功，跳转到Boot1处执行
}
else
{
// disable_watch_dog( ); // disable watch dog
msg("Fail in loading Boot1.\n"
"Jump to Fel.\n");
pll_reset();
__msdelay(10);
jump_to( FEL_BASE ); // 如果载入Boot1失败，将控制权交给Fel
}
}
void __CPU_ABT arm_abt()
{
mmu_disable();
printk("page_fault error: %bb at %x\n", __mmu_getfsr(), __mmu_getfar());
for (;;);
}
void init_memory_system(){
if(cpu_get_current() !=0){
scu_join_smp();
scu_enable_maintenance_broadcast();
}
/****************************************
* MMU
*/
// Disable MMU
mmu_disable();
// Initiate MMU - initiate the peripherals
mmu_init();
// Enable MMU
mmu_enable();
/****************************************
* Branch prediction
*/
// Disable branch prediction
arm_branch_prediction_disable();
// Invalidate branch prediction array
arm_branch_target_cache_invalidate();
// Branch Prediction Enable
arm_branch_prediction_enable();
/****************************************
* Data Cache
*/
// Disable L1 Data Caches
arm_dcache_disable();
// Invalidate Data cache
arm_dcache_invalidate();
// Enable Data cache
arm_dcache_enable();
/****************************************
* Instruction Cache
*/
// Disable L1 Instruction cache
arm_icache_disable();
// Invalidate Instruction cache
arm_icache_invalidate();
// Enable Instruction cache
arm_icache_enable();
/****************************************
* L2 Cache
*/
if(cpu_get_current() == 0){
// Disable L2
_l2c310_cache_disable();
// Set up L2 cache
_l2c310_cache_setup();
// Invalidate L2 cache
_l2c310_cache_invalidate();
// Enable L2 cache
_l2c310_cache_enable();
scu_enable();
scu_join_smp();
}
}