static int esa_send_cmd_(u32 cmd_code, bool sram_only)
{
u32 cnt, val;
int ret;
si.isr_done = 0;
writel(cmd_code, si.mailbox + CMD_CODE); /* command */
writel(1, si.regs + SW_INTR_CA5); /* trigger ca5 */
si.fw_use_dram = sram_only ? false : true;
ret = wait_event_interruptible_timeout(esa_wq, si.isr_done, HZ / 2);
if (!ret) {
esa_err("%s: CMD(%08X) timed out!!!\n",
__func__, cmd_code);
esa_dump_fw_log();
si.fw_use_dram = true;
return -EBUSY;
}
cnt = msecs_to_loops(10);
while (--cnt) {
val = readl(si.regs + CA5_STATUS);
if (val & CA5_STATUS_WFI)
break;
cpu_relax();
}
si.fw_use_dram = false;
return 0;
}
static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
{
void __iomem *regs = sdd->regs;
unsigned long loops;
u32 val;
writel(0, regs + S3C64XX_SPI_PACKET_CNT);
val = readl(regs + S3C64XX_SPI_CH_CFG);
val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
writel(val, regs + S3C64XX_SPI_CH_CFG);
val = readl(regs + S3C64XX_SPI_CH_CFG);
val |= S3C64XX_SPI_CH_SW_RST;
val &= ~S3C64XX_SPI_CH_HS_EN;
writel(val, regs + S3C64XX_SPI_CH_CFG);
/* Flush TxFIFO*/
loops = msecs_to_loops(1);
do {
val = readl(regs + S3C64XX_SPI_STATUS);
} while (TX_FIFO_LVL(val, sdd) && loops--);
if (loops == 0)
dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
/* Flush RxFIFO*/
loops = msecs_to_loops(1);
do {
val = readl(regs + S3C64XX_SPI_STATUS);
if (RX_FIFO_LVL(val, sdd))
readl(regs + S3C64XX_SPI_RX_DATA);
else
break;
} while (loops--);
if (loops == 0)
dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
val = readl(regs + S3C64XX_SPI_CH_CFG);
val &= ~S3C64XX_SPI_CH_SW_RST;
writel(val, regs + S3C64XX_SPI_CH_CFG);
val = readl(regs + S3C64XX_SPI_MODE_CFG);
val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
writel(val, regs + S3C64XX_SPI_MODE_CFG);
}
static cycle_t vt8500_timer_read(struct clocksource *cs)
{
int loops = msecs_to_loops(10);
writel(3, regbase + TIMER_CTRL_VAL);
while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
&& --loops)
cpu_relax();
return readl(regbase + TIMER_COUNT_VAL);
}
static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask)
{
int loops = msecs_to_loops(10);
while ((readb(reg) & bitmask) && --loops)
cpu_relax();
if (unlikely(!loops))
pr_warn("Waiting for status bits 0x%x to clear timed out\n",
bitmask);
}
static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
{
int loops = msecs_to_loops(10);
u32 mask = bitmask << (nr << 8);
while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
cpu_relax();
if (unlikely(!loops))
dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
mask);
}
static int vt8500_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
int loops = msecs_to_loops(10);
cycle_t alarm = clocksource.read(&clocksource) + cycles;
while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
&& --loops)
cpu_relax();
writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
if ((signed)(alarm - clocksource.read(&clocksource)) <= MIN_OSCR_DELTA)
return -ETIME;
writel(1, regbase + TIMER_IER_VAL);
return 0;
}
/*
* Wait for the LR signal to allow synchronisation to the L/R clock
* from the codec. May only be needed for slave mode.
*/
static int s5p_snd_lrsync(void)
{
u32 iiscon;
unsigned long loops = msecs_to_loops(1);
pr_debug("Entered %s\n", __func__);
while (--loops) {
iiscon = readl(s5p_i2s0_regs + S3C2412_IISCON);
if (iiscon & S3C2412_IISCON_LRINDEX)
break;
cpu_relax();
}
if (!loops) {
pr_debug("%s: timeout\n", __func__);
return -ETIMEDOUT;
}
return 0;
}
/*
* Wait for the LR signal to allow synchronisation to the L/R clock
* from the codec. May only be needed for slave mode.
*/
static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
{
u32 iiscon;
unsigned long loops = msecs_to_loops(5);
pr_debug("Entered %s\n", __func__);
while (--loops) {
iiscon = readl(i2s->regs + S3C2412_IISCON);
if (iiscon & S3C2412_IISCON_LRINDEX)
break;
cpu_relax();
}
if (!loops) {
printk(KERN_ERR "%s: timeout\n", __func__);
return -ETIMEDOUT;
}
return 0;
}
/*
* Wait for the LR signal to allow synchronisation to the L/R clock
* from the codec. May only be needed for slave mode.
*/
static int s3c_snd_lrsync(void)
{
u32 iiscon;
unsigned long loops = msecs_to_loops(5);
pr_debug("Entered %s\n", __func__);
while (--loops) {
iiscon = readl(lpam_i2s.regs + S3C_IISCON);
if (iiscon & S3C_IISCON_LRI)
break;
cpu_relax();
}
if (!loops) {
printk(KERN_ERR "%s: timeout\n", __func__);
return -ETIMEDOUT;
}
return 0;
}
static void esa_fw_shutdown(void)
{
u32 cnt, val;
if (!si.fw_ready)
return;
if (!si.fwmem_loaded)
return;
/* SUSPEND & IDLE */
esa_send_cmd(SYS_SUSPEND);
si.fw_suspended = false;
cnt = msecs_to_loops(100);
while (--cnt) {
val = readl(si.regs + CA5_STATUS);
if (val & CA5_STATUS_WFI) {
si.fw_suspended = true;
break;
}
cpu_relax();
}
esa_debug("CA5_STATUS: %X\n", val);
/* Backup SRAM */
memcpy(si.fwmem_sram_bak, si.sram, SRAM_FW_MAX);
#ifdef CONFIG_SND_SAMSUNG_SEIREN_OFFLOAD
memcpy(si.mailbox_bak, si.mailbox, 128);
#endif
/* power off */
esa_debug("Turn off CA5...\n");
lpass_reset(LPASS_IP_CA5, LPASS_OP_RESET);
si.fw_ready = false;
si.fw_use_dram = false;
}
