void __init msm_init_irq(void)
{
unsigned n;
/* select level interrupts */
writel(0, VIC_INT_TYPE0);
writel(0, VIC_INT_TYPE1);
/* select highlevel interrupts */
writel(0, VIC_INT_POLARITY0);
writel(0, VIC_INT_POLARITY1);
/* select IRQ for all INTs */
writel(0, VIC_INT_SELECT0);
writel(0, VIC_INT_SELECT1);
/* disable all INTs */
writel(0, VIC_INT_EN0);
writel(0, VIC_INT_EN1);
/* don't use 1136 vic */
writel(0, VIC_CONFIG);
/* enable interrupt controller */
writel(3, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
set_irq_chip(n, &msm_irq_chip);
set_irq_handler(n, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
msm_init_sirc();
}
void __init msm_init_irq(void)
{
unsigned n;
writel(0, VIC_INT_TYPE0);
writel(0, VIC_INT_TYPE1);
writel(0, VIC_INT_POLARITY0);
writel(0, VIC_INT_POLARITY1);
writel(0, VIC_INT_SELECT0);
writel(0, VIC_INT_SELECT1);
writel(0, VIC_INT_EN0);
writel(0, VIC_INT_EN1);
writel(0, VIC_CONFIG);
writel(3, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) {
irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
set_irq_flags(n, IRQF_VALID);
}
msm_init_sirc();
}
static void __init qsd8x50_init_irq(void)
{
msm_init_irq();
msm_init_sirc();
}
static void __init fsm9xxx_init_irq(void)
{
msm_init_irq();
msm_init_sirc();
}
