static void gic_unmask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); spin_lock(&irq_controller_lock); writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4); spin_unlock(&irq_controller_lock); msm_mpm_enable_irq(irq, 1); }
static void gic_mask_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); spin_lock(&irq_controller_lock); writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); spin_unlock(&irq_controller_lock); #ifdef CONFIG_MSM_MPM msm_mpm_enable_irq(irq, 0); #endif }
static void gic_disable_irq(unsigned int irq) { msm_mpm_enable_irq(irq, 0); }