void platform_secondary_init(unsigned int cpu)
{
pr_debug("CPU%u: Booted secondary processor\n", cpu);
WARN_ON(msm_platform_secondary_init(cpu));
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
/* clear the IPC1(SPI-8) pending SPI */
if (power_collapsed) {
raise_clear_spi(1, false);
clear_pending_spi(MSM8625_INT_ACSR_MP_CORE_IPC1);
power_collapsed = 0;
}
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void __cpuinit msm_secondary_init(unsigned int cpu)
{
WARN_ON(msm_platform_secondary_init(cpu));
write_pen_release(-1);
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void platform_secondary_init(unsigned int cpu)
{
WARN_ON(msm_platform_secondary_init(cpu));
gic_secondary_init(0);
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void __cpuinit msm_secondary_init(unsigned int cpu)
{
WARN_ON(msm_platform_secondary_init(cpu));
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void platform_secondary_init(unsigned int cpu)
{
WARN_ON(msm_platform_secondary_init(cpu));
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
/* Initialization routine for secondary CPUs after they are brought out of
* reset.
*/
void __cpuinit platform_secondary_init(unsigned int cpu)
{
pr_debug("CPU%u: Booted secondary processor\n", cpu);
WARN_ON(msm_platform_secondary_init(cpu));
trace_hardirqs_off();
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* RUMI does not adhere to GIC spec by enabling STIs by default.
* Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
*/
if (!machine_is_msm8x60_sim())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
gic_secondary_init(0);
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
pr_debug("CPU%u: Booted secondary processor\n", cpu);
WARN_ON(msm_platform_secondary_init(cpu));
gic_secondary_init(0);
write_pen_release(-1);
if (per_cpu(power_collapsed, cpu)) {
raise_clear_spi(cpu, false);
clear_pending_spi(cpu_data[cpu].ipc_irq);
per_cpu(power_collapsed, cpu) = 0;
}
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void __cpuinit platform_secondary_init(unsigned int cpu)
{
WARN_ON(msm_platform_secondary_init(cpu));
/*
* if any interrupts are already enabled for the primary
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
gic_secondary_init(0);
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
void __cpuinit msm8625_platform_secondary_init(unsigned int cpu)
{
WARN_ON(msm_platform_secondary_init(cpu));
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
/* clear the IPC pending SPI */
if (per_cpu(power_collapsed, cpu)) {
raise_clear_spi(cpu, false);
clear_pending_spi(cpu_data[cpu].ipc_irq);
per_cpu(power_collapsed, cpu) = 0;
}
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}