static void msm_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { unsigned long flags; unsigned int baud, mr; spin_lock_irqsave(&port->lock, flags); /* calculate and set baud rate */ baud = uart_get_baud_rate(port, termios, old, 300, 115200); baud = msm_set_baud_rate(port, baud); if (tty_termios_baud_rate(termios)) tty_termios_encode_baud_rate(termios, baud, baud); /* calculate parity */ mr = msm_read(port, UART_MR2); mr &= ~UART_MR2_PARITY_MODE; if (termios->c_cflag & PARENB) { if (termios->c_cflag & PARODD) mr |= UART_MR2_PARITY_MODE_ODD; else if (termios->c_cflag & CMSPAR) mr |= UART_MR2_PARITY_MODE_SPACE; else mr |= UART_MR2_PARITY_MODE_EVEN; } /* calculate bits per char */ mr &= ~UART_MR2_BITS_PER_CHAR; switch (termios->c_cflag & CSIZE) { case CS5: mr |= UART_MR2_BITS_PER_CHAR_5; break; case CS6: mr |= UART_MR2_BITS_PER_CHAR_6; break; case CS7: mr |= UART_MR2_BITS_PER_CHAR_7; break; case CS8: default: mr |= UART_MR2_BITS_PER_CHAR_8; break; } /* calculate stop bits */ mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); if (termios->c_cflag & CSTOPB) mr |= UART_MR2_STOP_BIT_LEN_TWO; else mr |= UART_MR2_STOP_BIT_LEN_ONE; /* set parity, bits per char, and stop bit */ msm_write(port, mr, UART_MR2); /* calculate and set hardware flow control */ mr = msm_read(port, UART_MR1); mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); if (termios->c_cflag & CRTSCTS) { mr |= UART_MR1_CTS_CTL; mr |= UART_MR1_RX_RDY_CTL; } msm_write(port, mr, UART_MR1); /* Configure status bits to ignore based on termio flags. */ port->read_status_mask = 0; if (termios->c_iflag & INPCK) port->read_status_mask |= UART_SR_PAR_FRAME_ERR; if (termios->c_iflag & (BRKINT | PARMRK)) port->read_status_mask |= UART_SR_RX_BREAK; uart_update_timeout(port, termios->c_cflag, baud); spin_unlock_irqrestore(&port->lock, flags); }
static void handle_delta_cts(struct uart_port *port) { msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); port->icount.cts++; wake_up_interruptible(&port->state->port.delta_msr_wait); }
static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) { unsigned int baud_code, rxstale, watermark; switch (baud) { case 300: baud_code = UART_CSR_300; rxstale = 1; break; case 600: baud_code = UART_CSR_600; rxstale = 1; break; case 1200: baud_code = UART_CSR_1200; rxstale = 1; break; case 2400: baud_code = UART_CSR_2400; rxstale = 1; break; case 4800: baud_code = UART_CSR_4800; rxstale = 1; break; case 9600: baud_code = UART_CSR_9600; rxstale = 2; break; case 14400: baud_code = UART_CSR_14400; rxstale = 3; break; case 19200: baud_code = UART_CSR_19200; rxstale = 4; break; case 28800: baud_code = UART_CSR_28800; rxstale = 6; break; case 38400: baud_code = UART_CSR_38400; rxstale = 8; break; case 57600: baud_code = UART_CSR_57600; rxstale = 16; break; case 115200: default: baud_code = UART_CSR_115200; baud = 115200; rxstale = 31; break; } msm_write(port, baud_code, UART_CSR); /* RX stale watermark */ watermark = UART_IPR_STALE_LSB & rxstale; watermark |= UART_IPR_RXSTALE_LAST; watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2); msm_write(port, watermark, UART_IPR); /* set RX watermark */ watermark = (port->fifosize * 3) / 4; msm_write(port, watermark, UART_RFWR); /* set TX watermark */ msm_write(port, 10, UART_TFWR); return baud; }
static int msm_startup(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); unsigned int data, rfr_level; int ret; snprintf(msm_port->name, sizeof(msm_port->name), "msm_serial%d", port->line); ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH, msm_port->name, port); if (unlikely(ret)) return ret; msm_init_clock(port); if (likely(port->fifosize > 12)) rfr_level = port->fifosize - 12; else rfr_level = port->fifosize; /* set automatic RFR level */ data = msm_read(port, UART_MR1); data &= ~UART_MR1_AUTO_RFR_LEVEL1; data &= ~UART_MR1_AUTO_RFR_LEVEL0; data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2); data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; msm_write(port, data, UART_MR1); /* make sure that RXSTALE count is non-zero */ data = msm_read(port, UART_IPR); if (unlikely(!data)) { data |= UART_IPR_RXSTALE_LAST; data |= UART_IPR_STALE_LSB; msm_write(port, data, UART_IPR); } data = 0; if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) { msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); msm_reset(port); data = UART_CR_TX_ENABLE; } data |= UART_CR_RX_ENABLE; msm_write(port, data, UART_CR); /* enable TX & RX */ /* Make sure IPR is not 0 to start with*/ if (msm_port->is_uartdm) msm_write(port, UART_IPR_STALE_LSB, UART_IPR); /* turn on RX and CTS interrupts */ msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | UART_IMR_CURRENT_CTS; if (msm_port->is_uartdm) { msm_write(port, 0xFFFFFF, UARTDM_DMRX); msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); } msm_write(port, msm_port->imr, UART_IMR); return 0; }
static int msm_startup(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); unsigned int data, rfr_level; int ret; snprintf(msm_port->name, sizeof(msm_port->name), "msm_serial%d", port->line); ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH, msm_port->name, port); if (unlikely(ret)) return ret; msm_init_clock(port); if (likely(port->fifosize > 12)) rfr_level = port->fifosize - 12; else rfr_level = port->fifosize; /* set automatic RFR level */ data = msm_read(port, UART_MR1); data &= ~UART_MR1_AUTO_RFR_LEVEL1; data &= ~UART_MR1_AUTO_RFR_LEVEL0; data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2); data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; msm_write(port, data, UART_MR1); /* make sure that RXSTALE count is non-zero */ data = msm_read(port, UART_IPR); if (unlikely(!data)) { data |= UART_IPR_RXSTALE_LAST; data |= UART_IPR_STALE_LSB; msm_write(port, data, UART_IPR); } msm_reset(port); msm_write(port, 0x05, UART_CR); /* enable TX & RX */ /* turn on RX and CTS interrupts */ msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | UART_IMR_CURRENT_CTS; msm_write(port, msm_port->imr, UART_IMR); #ifdef CONFIG_SERIAL_MSM_RX_WAKEUP if (use_low_power_wakeup(msm_port)) { ret = set_irq_wake(msm_port->wakeup.irq, 1); if (unlikely(ret)) return ret; ret = request_irq(msm_port->wakeup.irq, msm_rx_irq, IRQF_TRIGGER_FALLING, "msm_serial_wakeup", msm_port); if (unlikely(ret)) return ret; disable_irq(msm_port->wakeup.irq); } #endif return 0; }
static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) { unsigned int baud_code, rxstale, watermark; struct msm_port *msm_port = UART_TO_MSM(port); switch (baud) { case 300: baud_code = UART_CSR_300; rxstale = 1; break; case 600: baud_code = UART_CSR_600; rxstale = 1; break; case 1200: baud_code = UART_CSR_1200; rxstale = 1; break; case 2400: baud_code = UART_CSR_2400; rxstale = 1; break; case 4800: baud_code = UART_CSR_4800; rxstale = 1; break; case 9600: baud_code = UART_CSR_9600; rxstale = 2; break; case 14400: baud_code = UART_CSR_14400; rxstale = 3; break; case 19200: baud_code = UART_CSR_19200; rxstale = 4; break; case 28800: baud_code = UART_CSR_28800; rxstale = 6; break; case 38400: baud_code = UART_CSR_38400; rxstale = 8; break; case 57600: baud_code = UART_CSR_57600; rxstale = 16; break; case 115200: default: baud_code = UART_CSR_115200; baud = 115200; rxstale = 31; break; } if (msm_port->is_uartdm) msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); msm_write(port, baud_code, UART_CSR); /* RX stale watermark */ watermark = UART_IPR_STALE_LSB & rxstale; watermark |= UART_IPR_RXSTALE_LAST; watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2); msm_write(port, watermark, UART_IPR); /* set RX watermark */ watermark = (port->fifosize * 3) / 4; msm_write(port, watermark, UART_RFWR); /* set TX watermark */ msm_write(port, 10, UART_TFWR); if (msm_port->is_uartdm) { msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); msm_write(port, 0xFFFFFF, UARTDM_DMRX); msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); } return baud; }
static void reset_dm_count(struct uart_port *port) { wait_for_xmitr(port, UART_ISR_TX_READY); msm_write(port, 1, UARTDM_NCF_TX); }
static void msm_init_clock(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); clk_enable(msm_port->clk); #ifdef CONFIG_SERIAL_MSM_CLOCK_CONTROL msm_port->clk_state = MSM_CLK_ON; #endif #if 0 if (port->uartclk == 19200000) { /* clock is TCXO (19.2MHz) */ msm_write(port, 0x06, UART_MREG); msm_write(port, 0xF1, UART_NREG); msm_write(port, 0x0F, UART_DREG); msm_write(port, 0x1A, UART_MNDREG); } else { /* clock must be TCXO/4 */ msm_write(port, 0x18, UART_MREG); msm_write(port, 0xF6, UART_NREG); msm_write(port, 0x0F, UART_DREG); msm_write(port, 0x0A, UART_MNDREG); } #endif msm_write(port, 0xC0, UART_MREG); msm_write(port, 0xAF, UART_NREG); msm_write(port, 0x80, UART_DREG); msm_write(port, 0x19, UART_MNDREG); }
static void debug_port_init(void) { /* reset everything */ msm_write(UART_CR_CMD_RESET_RX, UART_CR); msm_write(UART_CR_CMD_RESET_TX, UART_CR); msm_write(UART_CR_CMD_RESET_ERR, UART_CR); msm_write(UART_CR_CMD_RESET_BREAK_INT, UART_CR); msm_write(UART_CR_CMD_RESET_CTS, UART_CR); msm_write(UART_CR_CMD_SET_RFR, UART_CR); /* setup clock dividers */ #if defined(CONFIG_ARCH_QSD8X50) if (clk_get_rate(debug_clk) == 19200000) { /* clock is TCXO (19.2MHz) */ msm_write(0x06, UART_MREG); msm_write(0xF1, UART_NREG); msm_write(0x0F, UART_DREG); msm_write(0x1A, UART_MNDREG); } else { /* clock must be TCXO/4 */ msm_write(0xC0, UART_MREG); msm_write(0xB2, UART_NREG); msm_write(0x7D, UART_DREG); msm_write(0x1C, UART_MNDREG); } #else msm_write(0xC0, UART_MREG); msm_write(0xB2, UART_NREG); msm_write(0x7D, UART_DREG); msm_write(0x1C, UART_MNDREG); #endif msm_write(UART_CSR_115200, UART_CSR); /* rx interrupt on every character -- keep it simple */ msm_write(0, UART_RFWR); /* enable TX and RX */ msm_write(0x05, UART_CR); /* enable RX interrupt */ msm_write(UART_IMR_RXLEV, UART_IMR); }
static inline void debug_putc(unsigned int c) { while (!(msm_read(UART_SR) & UART_SR_TX_READY)) ; msm_write(c, UART_TF); }