/*
* cpu_pdn:
* true = CPU dormant
* false = CPU standby
* pwrlevel:
* 0 = AXI is off
* 1 = AXI is 26M
* pwake_time:
* >= 0 = specific wakeup period
*/
wake_reason_t spm_go_to_sleep_dpidle(u32 spm_flags, u32 spm_data)
{
u32 sec = 0;
int wd_ret;
struct wake_status wakesta;
unsigned long flags;
struct mtk_irq_mask mask;
struct wd_api *wd_api;
static wake_reason_t last_wr = WR_NONE;
struct pcm_desc *pcmdesc = __spm_dpidle.pcmdesc;
struct pwr_ctrl *pwrctrl = __spm_dpidle.pwrctrl;
set_pwrctrl_pcm_flags(pwrctrl, spm_flags);
#if SPM_PWAKE_EN
sec = spm_get_wake_period(-1 /* FIXME */, last_wr);
#endif
pwrctrl->timer_val = sec * 32768;
pwrctrl->wake_src = spm_get_sleep_wakesrc();
wd_ret = get_wd_api(&wd_api);
if (!wd_ret)
wd_api->wd_suspend_notify();
spin_lock_irqsave(&__spm_lock, flags);
mt_irq_mask_all(&mask);
mt_irq_unmask_for_sleep(MT_SPM_IRQ_ID);
mt_cirq_clone_gic();
mt_cirq_enable();
/* set PMIC WRAP table for deepidle power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
spm_crit2("sleep_deepidle, sec = %u, wakesrc = 0x%x [%u]\n",
sec, pwrctrl->wake_src, is_cpu_pdn(pwrctrl->pcm_flags));
__spm_reset_and_init_pcm(pcmdesc);
__spm_kick_im_to_fetch(pcmdesc);
if (request_uart_to_sleep()) {
last_wr = WR_UART_BUSY;
goto RESTORE_IRQ;
}
__spm_init_pcm_register();
__spm_init_event_vector(pcmdesc);
__spm_set_power_control(pwrctrl);
__spm_set_wakeup_event(pwrctrl);
__spm_kick_pcm_to_run(pwrctrl);
spm_trigger_wfi_for_dpidle(pwrctrl);
__spm_get_wakeup_status(&wakesta);
__spm_clean_after_wakeup();
request_uart_to_wakeup();
last_wr = __spm_output_wake_reason(&wakesta, pcmdesc, true);
RESTORE_IRQ:
/* set PMIC WRAP table for normal power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
mt_cirq_flush();
mt_cirq_disable();
mt_irq_mask_restore(&mask);
spin_unlock_irqrestore(&__spm_lock, flags);
if (!wd_ret)
wd_api->wd_resume_notify();
return last_wr;
}
wake_reason_t spm_go_to_dpidle(u32 spm_flags, u32 spm_data)
{
struct wake_status wakesta;
unsigned long flags;
struct mtk_irq_mask mask;
wake_reason_t wr = WR_NONE;
struct pcm_desc *pcmdesc = __spm_dpidle.pcmdesc;
struct pwr_ctrl *pwrctrl = __spm_dpidle.pwrctrl;
#if SPM_AEE_RR_REC
aee_rr_rec_deepidle_val(1<<SPM_DEEPIDLE_ENTER);
#endif
/* Workaround: do NOT lower VPROC for turbo mode */
/* Workaround (2015.04.17): do NOT lower VPROC for FW v0.2.5 */
#if 0
if (is_ext_buck_exist())
#endif
spm_flags |= SPM_CPU_DVS_DIS;
set_pwrctrl_pcm_flags(pwrctrl, spm_flags);
//pwrctrl->timer_val = 1 * 32768;
spm_dpidle_before_wfi();
lockdep_off();
spin_lock_irqsave(&__spm_lock, flags);
mt_irq_mask_all(&mask);
mt_irq_unmask_for_sleep(SPM_IRQ0_ID);
mt_cirq_clone_gic();
mt_cirq_enable();
__spm_enable_i2c4_clk();
#if SPM_AEE_RR_REC
aee_rr_rec_deepidle_val(aee_rr_curr_deepidle_val()|(1<<SPM_DEEPIDLE_ENTER_UART_SLEEP));
#endif
if (request_uart_to_sleep()) {
wr = WR_UART_BUSY;
goto RESTORE_IRQ;
}
__spm_reset_and_init_pcm(pcmdesc);
__spm_kick_im_to_fetch(pcmdesc);
__spm_init_pcm_register();
__spm_init_event_vector(pcmdesc);
__spm_set_power_control(pwrctrl);
__spm_set_wakeup_event(pwrctrl);
spm_dpidle_pre_process();
__spm_kick_pcm_to_run(pwrctrl);
#if SPM_AEE_RR_REC
aee_rr_rec_deepidle_val(aee_rr_curr_deepidle_val()|(1<<SPM_DEEPIDLE_ENTER_WFI));
#endif
#ifdef SPM_DEEPIDLE_PROFILE_TIME
gpt_get_cnt(SPM_PROFILE_APXGPT,&dpidle_profile[1]);
#endif
spm_trigger_wfi_for_dpidle(pwrctrl);
#ifdef SPM_DEEPIDLE_PROFILE_TIME
gpt_get_cnt(SPM_PROFILE_APXGPT,&dpidle_profile[2]);
#endif
#if SPM_AEE_RR_REC
aee_rr_rec_deepidle_val(aee_rr_curr_deepidle_val()|(1<<SPM_DEEPIDLE_LEAVE_WFI));
#endif
spm_dpidle_post_process();
__spm_get_wakeup_status(&wakesta);
__spm_clean_after_wakeup();
#if SPM_AEE_RR_REC
aee_rr_rec_deepidle_val(aee_rr_curr_deepidle_val()|(1<<SPM_DEEPIDLE_ENTER_UART_AWAKE));
#endif
request_uart_to_wakeup();
wr = spm_output_wake_reason(&wakesta, pcmdesc);
__spm_disable_i2c4_clk();
RESTORE_IRQ:
mt_cirq_flush();
mt_cirq_disable();
mt_irq_mask_restore(&mask);
spin_unlock_irqrestore(&__spm_lock, flags);
lockdep_on();
spm_dpidle_after_wfi();
#if SPM_AEE_RR_REC
aee_rr_rec_deepidle_val(0);
#endif
return wr;
}
wake_reason_t spm_go_to_dpidle(u32 spm_flags, u32 spm_data)
{
struct wake_status wakesta;
unsigned long flags;
struct mtk_irq_mask mask;
wake_reason_t wr = WR_NONE;
struct pcm_desc *pcmdesc = __spm_dpidle.pcmdesc;
struct pwr_ctrl *pwrctrl = __spm_dpidle.pwrctrl;
struct spm_lp_scen *lpscen;
lpscen = spm_check_talking_get_lpscen(&__spm_dpidle, &spm_flags);
pcmdesc = lpscen->pcmdesc;
pwrctrl = lpscen->pwrctrl;
set_pwrctrl_pcm_flags(pwrctrl, spm_flags);
/* set PMIC WRAP table for deepidle power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
spin_lock_irqsave(&__spm_lock, flags);
mt_irq_mask_all(&mask);
mt_irq_unmask_for_sleep(MT_SPM_IRQ_ID);
mt_cirq_clone_gic();
mt_cirq_enable();
if (request_uart_to_sleep()) {
wr = WR_UART_BUSY;
goto RESTORE_IRQ;
}
__spm_reset_and_init_pcm(pcmdesc);
__spm_kick_im_to_fetch(pcmdesc);
__spm_init_pcm_register();
__spm_init_event_vector(pcmdesc);
__spm_set_power_control(pwrctrl);
__spm_set_wakeup_event(pwrctrl);
__spm_kick_pcm_to_run(pwrctrl);
spm_dpidle_before_wfi();
spm_trigger_wfi_for_dpidle(pwrctrl);
spm_dpidle_after_wfi();
__spm_get_wakeup_status(&wakesta);
__spm_clean_after_wakeup();
request_uart_to_wakeup();
wr = __spm_output_wake_reason(&wakesta, pcmdesc, false);
RESTORE_IRQ:
mt_cirq_flush();
mt_cirq_disable();
mt_irq_mask_restore(&mask);
spin_unlock_irqrestore(&__spm_lock, flags);
/* set PMIC WRAP table for normal power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
return wr;
}
void spm_go_to_sodi(u32 spm_flags, u32 spm_data)
{
struct wake_status wakesta;
unsigned long flags;
struct mtk_irq_mask mask;
wake_reason_t wr = WR_NONE;
struct pcm_desc *pcmdesc = __spm_sodi.pcmdesc;
struct pwr_ctrl *pwrctrl = __spm_sodi.pwrctrl;
#if SPM_AEE_RR_REC
aee_rr_rec_sodi_val(1<<SPM_SODI_ENTER);
#endif
set_pwrctrl_pcm_flags(pwrctrl, spm_flags);
/* set PMIC WRAP table for deepidle power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_SODI);
soidle_before_wfi(0);
lockdep_off();
spin_lock_irqsave(&__spm_lock, flags);
mt_irq_mask_all(&mask);
mt_irq_unmask_for_sleep(SPM_IRQ0_ID/*MT_SPM_IRQ_ID*/);
mt_cirq_clone_gic();
mt_cirq_enable();
#if SPM_AEE_RR_REC
aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_SPM_FLOW));
#endif
__spm_reset_and_init_pcm(pcmdesc);
#if 0
/* 0: mempll shutdown mode; 1: cg mode */
gSpm_SODI_mempll_pwr_mode ? (pwrctrl->pcm_flags |= SPM_MEMPLL_CPU) :
(pwrctrl->pcm_flags &= ~SPM_MEMPLL_CPU);
#endif
__spm_kick_im_to_fetch(pcmdesc);
__spm_init_pcm_register();
__spm_init_event_vector(pcmdesc);
/* set pcm_apsrc_req to be 1 if 10006b0c[0] is 1 */
if ((spm_read(SPM_PCM_SRC_REQ) & 1) || pwrctrl->pcm_apsrc_req)
pwrctrl->pcm_apsrc_req = 1;
else
pwrctrl->pcm_apsrc_req = 0;
__spm_set_power_control(pwrctrl);
__spm_set_wakeup_event(pwrctrl);
/* set pcm_flags[18] to be 1 if 10006b08[7] is 1 */
if ((spm_read(SPM_PCM_FLAGS) & SPM_MEMPLL_RESET) ||
gSpm_SODI_mempll_pwr_mode ||
(pwrctrl->pcm_flags_cust & SPM_MEMPLL_CPU))
pwrctrl->pcm_flags |= SPM_MEMPLL_CPU;
else
pwrctrl->pcm_flags &= ~SPM_MEMPLL_CPU;
__spm_kick_pcm_to_run(pwrctrl);
#if SPM_AEE_RR_REC
aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_ENTER_WFI));
#endif
spm_trigger_wfi_for_sodi(pwrctrl);
#if SPM_AEE_RR_REC
aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_LEAVE_WFI));
#endif
__spm_get_wakeup_status(&wakesta);
__spm_clean_after_wakeup();
wr = __spm_output_wake_reason(&wakesta, pcmdesc, false);
/* for test */
/* wr = __spm_output_wake_reason(&wakesta, pcmdesc, true); */
#if SPM_AEE_RR_REC
aee_rr_rec_sodi_val(aee_rr_curr_sodi_val()|(1<<SPM_SODI_LEAVE_SPM_FLOW));
#endif
mt_cirq_flush();
mt_cirq_disable();
mt_irq_mask_restore(&mask);
spin_unlock_irqrestore(&__spm_lock, flags);
lockdep_on();
soidle_after_wfi(0);
/* set PMIC WRAP table for normal power control */
mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_NORMAL);
#if SPM_AEE_RR_REC
aee_rr_rec_sodi_val(0);
#endif
//return wr;
}
