void bl31_platform_setup(void)
{
platform_setup_cpu();
generic_delay_timer_init();
plat_mt_gic_driver_init();
/* Initialize the gic cpu and distributor interfaces */
plat_mt_gic_init();
/* Topologies are best known to the platform. */
mt_setup_topology();
}
/*******************************************************************************
* Perform any BL3-1 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
platform_setup_cpu();
platform_setup_sram();
plat_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
plat_mt_gic_init();
arm_gic_setup();
/* Topologies are best known to the platform. */
mt_setup_topology();
/* Initialize spm at boot time */
spm_boot_init();
}
/*******************************************************************************
* Perform any BL3-1 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
platform_setup_cpu();
platform_setup_sram();
generic_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
plat_arm_gic_driver_init();
plat_arm_gic_init();
#if ENABLE_PLAT_COMPAT
/* Topologies are best known to the platform. */
mt_setup_topology();
#endif
/* Initialize spm at boot time */
spm_boot_init();
}
/*******************************************************************************
* Initialize the gic, configure the CLCD and zero out variables needed by the
* secondaries to boot up correctly.
******************************************************************************/
void bl31_platform_setup()
{
// unsigned int reg_val;
/* Initialize the gic cpu and distributor interfaces */
gic_setup();
#if 0 //do not init CLCD in ATF
/*
* TODO: Configure the CLCD before handing control to
* linux. Need to see if a separate driver is needed
* instead.
*/
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
(1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
#endif
#if 0 //FIXME TIMER CTRL skip now
/* Enable and initialize the System level generic timer */
mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
/* Allow access to the System counter timer module */
reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1));
mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
#endif
/* Topologies are best known to the platform. */
mt_setup_topology();
}
