static void __init hdpu_setup_peripherals(void) { unsigned int val; mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0); mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3)); mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); /* Enable pipelining */ mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13)); /* Enable Snoop Pipelineing */ mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24)); /* * Change DRAM read buffer assignment. * Assign read buffer 0 dedicated only for CPU, * and the rest read buffer 1. */ val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG); val = val & 0x03ffffff; val = val | 0xf8000000; mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val); /* * Configure internal SRAM - * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set * Parity enabled. * Parity error propagation * Arbitration not parked for CPU only * Other bits are reserved. */ #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); #else mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0); #endif hdpu_intr_setup(); }
void __init ev64360_setup_peripherals(void) { u32 base; /* Set up window for boot CS */ mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); /* We only use the 32-bit flash */ mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base, &ev64360_flash_size_0); ev64360_flash_size_1 = 0; mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); TODC_INIT(TODC_TYPE_DS1501, 0, 0, ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8); mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); /* Set up Enet->SRAM window */ mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2); bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); /* Give enet r/w access to memory region */ mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1))); mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1))); mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1))); mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); #if defined(CONFIG_NOT_COHERENT_CACHE) mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000); #else mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); #endif /* * Setting the SRAM to 0. Note that this generates parity errors on * internal data path in SRAM since it's first time accessing it * while after reset it's not configured. */ memset(sram_base, 0, MV64360_SRAM_SIZE); /* set up PCI interrupt controller */ ev64360_intr_setup(); }
void __init katana_setup_peripherals(void) { u32 base; /* Set up windows for boot CS, soldered & socketed flash, and CPLD */ mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); /* Assume firmware set up window sizes correctly for dev 0 & 1 */ mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base, &katana_flash_size_0); if (katana_flash_size_0 > 0) { mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); } mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base, &katana_flash_size_1); if (katana_flash_size_1 > 0) { mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0), katana_flash_size_1, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); } mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE); mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); /* Set up Enet->SRAM window */ mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2); bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); /* Give enet r/w access to memory region */ mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1))); mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1))); mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1))); mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); /* Must wait until window set up before retrieving board id */ katana_get_board_id(); /* Enumerate pci bus (must know board id before getting proc number) */ if (katana_get_proc_num() == 0) bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0); #if defined(CONFIG_NOT_COHERENT_CACHE) mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000); #else mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); #endif /* * Setting the SRAM to 0. Note that this generates parity errors on * internal data path in SRAM since it's first time accessing it * while after reset it's not configured. */ memset(sram_base, 0, MV64360_SRAM_SIZE); /* Only processor zero [on 3750] is an PCI interrupt controller */ if (katana_get_proc_num() == 0) katana_intr_setup(); }
void __init chestnut_setup_peripherals(void) { mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); #ifdef CONFIG_NOT_COHERENT_CACHE mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0); #else mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); #endif sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); memset(sram_base, 0, MV64360_SRAM_SIZE); /* * Configure MPP pins for PCI DMA * * PCI Slot GNT pin REQ pin * 0 MPP16 MPP17 * 1 MPP18 MPP19 * 2 MPP20 MPP21 * 3 MPP22 MPP23 */ mv64x60_write(&bh, MV64x60_MPP_CNTL_2, (0x1 << 0) | /* MPPSel16 PCI0_GNT[0] */ (0x1 << 4) | /* MPPSel17 PCI0_REQ[0] */ (0x1 << 8) | /* MPPSel18 PCI0_GNT[1] */ (0x1 << 12) | /* MPPSel19 PCI0_REQ[1] */ (0x1 << 16) | /* MPPSel20 PCI0_GNT[2] */ (0x1 << 20) | /* MPPSel21 PCI0_REQ[2] */ (0x1 << 24) | /* MPPSel22 PCI0_GNT[3] */ (0x1 << 28)); /* MPPSel23 PCI0_REQ[3] */ /* * Set unused MPP pins for output, as per schematic note * * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06 * MPP09, MPP10, MPP13, MPP14, MPP15 */ mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0, (0xf << 4) | /* MPPSel01 GPIO[1] */ (0xf << 8) | /* MPPSel02 GPIO[2] */ (0xf << 16) | /* MPPSel04 GPIO[4] */ (0xf << 20) | /* MPPSel05 GPIO[5] */ (0xf << 24)); /* MPPSel06 GPIO[6] */ mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, (0xf << 4) | /* MPPSel09 GPIO[9] */ (0xf << 8) | /* MPPSel10 GPIO[10] */ (0xf << 20) | /* MPPSel13 GPIO[13] */ (0xf << 24) | /* MPPSel14 GPIO[14] */ (0xf << 28)); /* MPPSel15 GPIO[15] */ mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */ BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(6) | BIT(9) | BIT(10) | BIT(13) | BIT(14) | BIT(15)); /* * Configure the following MPP pins to indicate a level * triggered interrupt * * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset) * MPP25 - UART A (high) * MPP26 - UART B (high) * MPP28 - PCI Slot 3 (low) * MPP29 - PCI Slot 2 (low) * MPP30 - PCI Slot 1 (low) * MPP31 - PCI Slot 0 (low) */ mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, BIT(3) | BIT(2) | BIT(1) | BIT(0) | /* MPP 24 */ BIT(7) | BIT(6) | BIT(5) | BIT(4) | /* MPP 25 */ BIT(11) | BIT(10) | BIT(9) | BIT(8) | /* MPP 26 */ BIT(19) | BIT(18) | BIT(17) | BIT(16) | /* MPP 28 */ BIT(23) | BIT(22) | BIT(21) | BIT(20) | /* MPP 29 */ BIT(27) | BIT(26) | BIT(25) | BIT(24) | /* MPP 30 */ BIT(31) | BIT(30) | BIT(29) | BIT(28)); /* MPP 31 */ /* * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low), * 31 (low) interrupt polarity input signal and level triggered */ mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26)); mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(28) | BIT(29) | BIT(30) | BIT(31)); mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) | BIT(31)); /* Config GPP interrupt controller to respond to level trigger */ mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10)); /* * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0 */ mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) | BIT(31))); mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) | BIT(31)); /* * Dismiss and then enable interrupt on CPU #0 high cause register * BIT27 summarizes GPP interrupts 24-31 */ mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27)); if (ppc_md.progress) ppc_md.progress("chestnut_setup_bridge: exit", 0); }