void __init mv_map_io(void)
{
MV_U32 id = mvBoardIdGet();
switch(id) {
case DB_78XX0_ID:
iotable_init(DB_78XX0_MEM_TABLE, ARRAY_SIZE(DB_78XX0_MEM_TABLE));
break;
case DB_78200_ID:
iotable_init(DB_78200_MEM_TABLE, ARRAY_SIZE(DB_78200_MEM_TABLE));
break;
case DB_632X_ID:
iotable_init(DB_632X_MEM_TABLE, ARRAY_SIZE(DB_632X_MEM_TABLE));
break;
case RD_78XX0_AMC_ID:
iotable_init(RD_78XX0_AMC_MEM_TABLE, ARRAY_SIZE(RD_78XX0_AMC_MEM_TABLE));
break;
case RD_78XX0_MASA_ID:
iotable_init(RD_78XX0_MASA_MEM_TABLE, ARRAY_SIZE(RD_78XX0_MASA_MEM_TABLE));
break;
case RD_78XX0_H3C_ID:
iotable_init(RD_78XX0_H3C_MEM_TABLE, ARRAY_SIZE(RD_78XX0_H3C_MEM_TABLE));
break;
default:
printk("ERROR: can't find system address map for board id 0x%X\n", id);
BUG();
}
}
/*******************************************************************************
* mvBoardSwitchSmiAddrGet - Get the the Ethernet Switch SMI address
*
* DESCRIPTION:
* This routine returns the Switch SMI address.
*
* INPUT:
* ethPortNum - Ethernet port number.
* switchIndex - Switch index.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR - if ethPortNum or switchIndex are illegal or board is unknown
* The Switch SMI address, -1 if the port number is wrong or if not relevant.
*
*******************************************************************************/
MV_32 mvBoardSwitchSmiAddrGet(MV_U32 ethPortNum, MV_U32 switchIndex)
{
MV_U32 boardId = mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardSwitchSmiAddrGet: Board unknown.\n");
return MV_ERROR;
}
if (ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo)
{
mvOsPrintf("mvBoardSwitchSmiAddrGet: Illegal port number(%u)\n", ethPortNum);
return MV_ERROR;
}
if (switchIndex >= BOARD_MAX_CASCADED_SWITCHES)
{
mvOsPrintf("mvBoardSwitchSmiAddrGet: Illegal Switch index(%u)\n", switchIndex);
return MV_ERROR;
}
if ((MV_32)(BOARD_INFO(boardId)->pSwitchInfo))
return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchSmiAddr[switchIndex];
return MV_ERROR;
}
/*******************************************************************************
* mvBoardSwitchPortGet - Get the mapping between the board connector (logical port number) and the
* physical Switch port
*
* DESCRIPTION:
* This routine returns the matching Switch port.
*
* INPUT:
* ethPortNum - Ethernet port number.
* logicalPortNum - logical number of the connector on the board
*
* OUTPUT:
* switchIndex - Switch index.
* portNum - Switch port number.
* portName - Switch port name (string)
*
* RETURN:
* MV_OK on success, MV_ERROR otherwise.
*
*******************************************************************************/
MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 logicalPortNum, MV_32 *switchIndex, MV_32 *portNum, char *portName)
{
MV_U32 boardId = mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n");
return MV_ERROR;
}
if (logicalPortNum >= BOARD_ETH_SWITCH_PORT_NUM)
{
mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n");
return MV_ERROR;
}
if ((switchIndex == NULL) || (portNum == NULL))
{
mvOsPrintf("mvBoardSwitchPortGet: got NULL arguments.\n");
return MV_ERROR;
}
if ((MV_32)(BOARD_INFO(boardId)->pSwitchInfo))
{
*switchIndex = BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[logicalPortNum].qdSwitchNum;
*portNum = BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[logicalPortNum].qdPortNum;
memcpy(portName, BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[logicalPortNum].portStr, BOARD_ETH_MAX_PORT_STRING);
return MV_OK;
}
return MV_ERROR;
}
static int mv_rtc_init(void)
{
MV_RTC_TIME time;
struct timespec tv;
switch(mvBoardIdGet()) {
case RD_88F5181L_VOIP_FXO_GE:
case RD_88W8660_AP82S_DDR1:
return 0;
}
mvRtcDS1339TimeGet(&time);
/* check if the year is invalid - bigger than 2038 */
if (time.year >= 38) {
time.year=0;
mvRtcDS1339TimeSet(&time);
printk(KERN_INFO "RTC has been updated!!!");
}
tv.tv_nsec = 0;
/* same as in the U-Boot we use the year for century 20 only */
tv.tv_sec = mktime ( time.year + 2000, time.month,
time.date, time.hours,
time.minutes, time.seconds);
do_settimeofday(&tv);
set_rtc = mv_set_rtc;
register_rtc(&rtc_ops);
printk("RTC registered\n");
return 0;
}
static int do_sar_default(void)
{
MV_U32 temp, defaultValue, boardIdIndex, boardId = mvBoardIdGet();
if (boardId != DB_6660_ID && boardId != DB_6650_ID) {
printf("\nError: S@R fields are readable only for current board\n");
return 1;
}
boardIdIndex = mvBoardIdIndexGet(boardId);
defaultValue = boardSatrDefault[MV_SATR_CPU_DDR_L2_FREQ].defauleValueForBoard[boardIdIndex];
if (mvCtrlSatRRead(MV_SATR_CPU_DDR_L2_FREQ, &temp) == MV_OK )
mvCtrlSatRWrite(MV_SATR_CPU_DDR_L2_FREQ, defaultValue, MV_TRUE);
defaultValue = boardSatrDefault[MV_SATR_CORE_CLK_SELECT].defauleValueForBoard[boardIdIndex];
if (defaultValue == _200MHz)
defaultValue = 0x1;
else
defaultValue = 0x0;
if (mvCtrlSatRRead(MV_SATR_CORE_CLK_SELECT, &temp) == MV_OK )
mvCtrlSatRWrite(MV_SATR_CORE_CLK_SELECT, defaultValue, MV_TRUE);
defaultValue = boardSatrDefault[MV_SATR_CPU1_ENABLE].defauleValueForBoard[boardIdIndex];
if (defaultValue == MV_TRUE)
defaultValue = 0x1;
else
defaultValue = 0x0;
if (mvCtrlSatRRead(MV_SATR_CPU1_ENABLE, &temp) == MV_OK )
mvCtrlSatRWrite(MV_SATR_CPU1_ENABLE, defaultValue, MV_TRUE);
defaultValue = boardSatrDefault[MV_SATR_SSCG_DISABLE].defauleValueForBoard[boardIdIndex];
if (defaultValue == MV_TRUE)
defaultValue = 0x1;
else
defaultValue = 0x0;
if (mvCtrlSatRRead(MV_SATR_SSCG_DISABLE, &temp) == MV_OK )
mvCtrlSatRWrite(MV_SATR_SSCG_DISABLE, defaultValue, MV_TRUE);
defaultValue = boardSatrDefault[MV_SATR_PEX0_CLOCK].defauleValueForBoard[boardIdIndex];
if (defaultValue == MV_TRUE)
defaultValue = 0x1;
else
defaultValue = 0x0;
if (mvCtrlSatRRead(MV_SATR_PEX0_CLOCK, &temp) == MV_OK )
mvCtrlSatRWrite(MV_SATR_PEX0_CLOCK, defaultValue, MV_TRUE);
defaultValue = boardSatrDefault[MV_SATR_PEX1_CLOCK].defauleValueForBoard[boardIdIndex];
if (defaultValue == MV_TRUE)
defaultValue = 0x1;
else
defaultValue = 0x0;
if (mvCtrlSatRRead(MV_SATR_PEX1_CLOCK, &temp) == MV_OK )
mvCtrlSatRWrite(MV_SATR_PEX1_CLOCK, defaultValue, MV_TRUE);
printf("\nSample at Reset values were restored to default.\n");
return 0;
}
/*******************************************************************************
* driverConfig
*
* DESCRIPTION:
* This function initializes the driver level of the quarterDeck software.
*
* INPUTS:
* None.
* OUTPUTS:
* None.
* RETURNS:
* GT_OK - on success, or
* GT_OUT_OF_CPU_MEM - if failed to allocate CPU memory,
* GT_FAIL - otherwise.
*
* COMMENTS:
* 1. This function should perform the following:
* - Initialize the global switch configuration structure.
* - Initialize Mii Interface
*
*******************************************************************************/
GT_STATUS driverConfig
(
IN GT_QD_DEV *dev
)
{
GT_U16 deviceId;
#ifdef CONFIG_ARCH_FEROCEON_KW
GT_U16 tmp, phy;
#endif
GT_BOOL highSmiDevAddr;
if(dev->accessMode == SMI_AUTO_SCAN_MODE)
{
/* Initialize the MII / SMI interface, search for the device */
if((deviceId = miiSmiIfInit(dev,&highSmiDevAddr)) == 0)
{
return GT_FAIL;
}
dev->baseRegAddr = (highSmiDevAddr)?0x10:0;
}
else
{
if((deviceId = miiSmiManualIfInit(dev,(GT_U32)dev->baseRegAddr)) == 0)
{
return GT_FAIL;
}
}
/* Init the device's config struct. */
dev->deviceId = deviceId >> 4;
dev->revision = (GT_U8)deviceId & 0xF;
#ifdef CONFIG_ARCH_FEROCEON_KW
if(mvBoardIdGet() == RD_88F6281A_ID) {
/* Enable RGMII delay on Tx and Rx for CPU port */
miiSmiIfWriteRegister(dev, 0x14,0x1a, 0x81e7);
miiSmiIfReadRegister(dev, 0x15,0x1a,&tmp);
miiSmiIfWriteRegister(dev, 0x15,0x1a,0x18);
miiSmiIfWriteRegister(dev, 0x14,0x1a,0xc1e7);
/* swap MDI signals for PHYs 0,1,2,3,4 on RD_88F6281A_ID */
for(phy = 0; phy < 5; phy++) {
miiSmiIfWriteRegister(dev, 0x1c,0x19,0xf);
miiSmiIfWriteRegister(dev, 0x1c,0x18,(0x9414 + (phy*0x20)));
miiSmiIfReadRegister(dev, 0x1c, 0x19,&tmp); /* used for delay */
/* testing - read phy register #20
miiSmiIfWriteRegister(dev, 0x1c,0x18,(0x9814+ (phy*0x20)));
miiSmiIfReadRegister(dev, 0x1c, 0x19,&tmp);
DBG_INFO(("phy-%d reg20 = 0x%x\n",phy,tmp));
*/
}
}
#endif
return GT_OK;
}
int mv_pci_if_num_to_skip(void)
{
switch(mvBoardIdGet()) {
case DB_78XX0_ID:
case DB_78200_ID:
return 2;
case RD_78XX0_H3C_ID:
return 3;
default:
return -1;
}
}
void mv_leds_hearbeat(void)
{
u32 sec = jiffies_to_msecs(jiffies - last_jiffies) / 1000;
if (!sec)
return;
led_val = (led_val % (1 << mvBoardDebugLedNumGet(mvBoardIdGet())));
mvBoardDebugLed(led_val);
led_val++;
last_jiffies = jiffies;
}
/*******************************************************************************
* mvBoardPhyAddrGet - Get the phy address
*
* DESCRIPTION:
* This routine returns the Phy address of a given ethernet port.
*
* INPUT:
* ethPortNum - Ethernet port number.
*
* OUTPUT:
* None.
*
* RETURN:
* 32bit describing Phy address, -1 if the port number is wrong.
*
*******************************************************************************/
MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum)
{
MV_U32 boardId= mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n");
return MV_ERROR;
}
return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr;
}
/*******************************************************************************
* mvBoardUseDsaTagOnPort
*/
MV_BOOL mvBoardUseDsaTagOnPort(MV_U32 port)
{
MV_BOARD_INFO *b = BOARD_INFO(mvBoardIdGet());
if (port >= b->numBoardMacInfo)
{
mvOsPrintf("%s: Wrong port number (%u)\n", __func__, port);
return MV_ERROR;
}
return b->portDsaInfo[port].useDsaTag;
}
int __init mv_pm_init(void)
{
printk(KERN_INFO "Marvell Kirkwood Power Management Initializing\n");
/* supported for RD 88F6282A only */
if (mvBoardIdGet() != RD_88F6282A_ID) {
return 0;
}
suspend_set_ops(&mv_pm_ops);
mv_init_soft_reset();
return 0;
}
/*******************************************************************************
* mvBoardMacSpeedGet - Get the Mac speed
*
* DESCRIPTION:
* This routine returns the Mac speed if pre define of a given ethernet port.
*
* INPUT:
* ethPortNum - Ethernet port number.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BOARD_MAC_SPEED, -1 if the port number is wrong.
*
*******************************************************************************/
MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum)
{
MV_U32 boardId= mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n");
return MV_ERROR;
}
return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed;
}
/*******************************************************************************
**
** onuPonDyingGaspExit
** ____________________________________________________________________________
**
** DESCRIPTION: The function forces system reset after dying gasp
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonDyingGaspExit(void)
{
if (mvBoardIdGet() == DB_88F6535_BP_ID) {
mvPonPrint(PON_PRINT_INFO, PON_INIT_MODULE, "\n\n\n");
mvPonPrint(PON_PRINT_INFO, PON_INIT_MODULE, "=========================================\n");
mvPonPrint(PON_PRINT_INFO, PON_INIT_MODULE, "======= Dying Gasp Detected =============\n");
mvPonPrint(PON_PRINT_INFO, PON_INIT_MODULE, "======= System Need To Reboot !!!!! =====\n");
mvPonPrint(PON_PRINT_INFO, PON_INIT_MODULE, "=========================================\n");
}
return(MV_OK);
}
MV_VOID mvBoardEnvInit(MV_VOID)
{
MV_U32 boardId= mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardEnvInit:Board unknown.\n");
return;
}
if (mvBoardIdGet() != XCAT98DX_ID) {
/* Set NAND interface access parameters */
MV_REG_WRITE(NAND_READ_PARAMS_REG, BOARD_INFO(boardId)->nandFlashReadParams);
MV_REG_WRITE(NAND_WRITE_PARAMS_REG, BOARD_INFO(boardId)->nandFlashWriteParams);
MV_REG_WRITE(NAND_CTRL_REG, BOARD_INFO(boardId)->nandFlashControl);
}
/* Set GPP Out value */
MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow);
MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh);
/* set GPP polarity */
mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow);
mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh);
/* Workaround for Erratum FE-MISC-70*/
if(mvCtrlRevGet()==MV_88F6XXX_A0_REV)
{
BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd;
BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002;
} /*End of WA*/
/* Set GPP Out Enable*/
mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow);
mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh);
/* Nand CE */
MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT);
}
int mv_is_pci_io_mapped(int ifNum)
{
switch(mvBoardIdGet()) {
case DB_78XX0_ID:
case DB_78200_ID:
case DB_632X_ID:
case RD_78XX0_H3C_ID:
if (ifNum < mvCtrlPciIfMaxIfGet())
return 1;
default:
return 0;
}
}
static ssize_t mvBoardType(char *buf)
{
MV_U32 boardType;
int off = 0;
boardType = mvBoardIdGet();
if (boardType == DB_88F6535_BP_ID)
off += sprintf(buf+off, "db_board\n");
else if (boardType == RD_88F6510_SFU_ID)
off += sprintf(buf+off, "rd_board\n");
return off;
}
/*******************************************************************************
* mvBoardNameGet - Get Board name
*
* DESCRIPTION:
* This function returns a string describing the board model and revision.
* String is extracted from board I2C EEPROM.
*
* INPUT:
* None.
*
* OUTPUT:
* pNameBuff - Buffer to contain board name string. Minimum size 32 chars.
*
* RETURN:
*
* MV_ERROR if informantion can not be read.
*******************************************************************************/
MV_STATUS mvBoardNameGet(char *pNameBuff)
{
MV_U32 boardId= mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsSPrintf (pNameBuff, "Board unknown.\n");
return MV_ERROR;
}
mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName);
return MV_OK;
}
MV_CPU_DEC_WIN* mv_sys_map(void)
{
switch(mvBoardIdGet()) {
case DB_88F6710_BP_ID:
case RD_88F6710_ID:
#if defined(CONFIG_SYNO_ARMADA_ARCH)
case SYNO_DS213j_ID:
case SYNO_US3_ID:
case SYNO_RS214_ID:
#endif
return SYSMAP_ARMADA_370;
default:
printk("ERROR: can't find system address map\n");
return NULL;
}
}
static int __init leds_init(void)
{
switch(mvBoardIdGet()) {
/* when 7seg present */
case DB_88F5181L_DDR2_2XTDM:
case DB_88W8660_DDR2:
case DB_88F5182_DDR2:
case DB_88F5182_DDR2_A:
case DB_88F5181_5281_DDR1:
case DB_88F5181_5281_DDR2:
case DB_88F5X81_DDR2:
case DB_88F5X81_DDR1:
case DB_88F5082_DDR2:
use7seg = 1;
}
return 0;
}
/*******************************************************************************
* mvBoardSmiScanModeGet - Get Switch SMI scan mode
*
* DESCRIPTION:
* This routine returns Switch SMI scan mode.
*
* INPUT:
* ethPortNum - Ethernet port number.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR - if ethPortNum is illegal or board is unknown
* 1 for SMI_MANUAL_MODE,
* 2 for SMI_MULTI_ADDR_MODE,
* -1 if the port number is wrong or if not relevant.
*
*******************************************************************************/
MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum)
{
MV_U32 boardId = mvBoardIdGet();
if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID)))
{
mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n");
return MV_ERROR;
}
if (ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo)
{
mvOsPrintf("mvBoardSmiScanModeGet: Illegal port number(%u)\n", ethPortNum);
return MV_ERROR;
}
if ((MV_32)(BOARD_INFO(boardId)->pSwitchInfo))
return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode;
return MV_ERROR;
}
/*******************************************************************************
**
** onuPonDyingGaspProcess
** ____________________________________________________________________________
**
** DESCRIPTION: The function process dying gasp function, kill VoIP
**
** PARAMETERS: None
**
** OUTPUTS: None
**
** RETURNS: MV_OK or error
**
*******************************************************************************/
MV_STATUS onuPonDyingGaspProcess(void)
{
MV_STATUS status;
MV_U32 boardType;
/* GPON/EPON configuration of Dying Gasp */
/* ===================================== */
boardType = mvBoardIdGet();
switch (boardType) {
case RD_88F6510_SFU_ID:
case RD_88F6560_GW_ID:
case RD_88F6530_MDU_ID:
status = asicOntMiscRegWrite(mvAsicReg_PON_MPP_24, 0, 0); /* power down voip */
break;
default:
status = MV_ERROR;
}
return(status);
}
int do_sar_default(void)
{
MV_U32 i, rc, defaultValue, boardId = mvBoardIdIndexGet(mvBoardIdGet());
MV_SATR_TYPE_ID satrClassId;
MV_BOARD_SATR_INFO satrInfo;
MV_U32 satrBootDeviceValue = mvCtrlbootSrcGet(), tmp;
for (i = 0; i < MAX_DEFAULT_ENTRY; i++) {
satrClassId = boardSatrDefault[i].satrId;
if (mvBoardSatrInfoConfig(satrClassId, &satrInfo) != MV_OK)
continue;
if (satrClassId == MV_SATR_BOOT_DEVICE)
boardSatrDefault[i].defauleValueForBoard[boardId] = satrBootDeviceValue & satrInfo.mask;
if (satrClassId == MV_SATR_BOOT2_DEVICE) {
tmp = satrBootDeviceValue >> MV_SATR_BOOT2_VALUE_OFFSET;
boardSatrDefault[i].defauleValueForBoard[boardId] = tmp & MV_SATR_BOOT2_VALUE_MASK;
}
defaultValue = boardSatrDefault[i].defauleValueForBoard[boardId];
rc = mvBoardSatRWrite(satrClassId, defaultValue);
if (rc == MV_ERROR) {
mvOsPrintf("Error write S@R for id=%d\n", satrClassId);
}
}
MV_CPU_DEC_WIN* mv_sys_map(void)
{
switch(mvBoardIdGet()) {
case DB_78XX0_ID:
if (mvBoardIsBootFromNor32())
return SYSMAP_DB_78XX0_NOR_32BIT;
else
return SYSMAP_DB_78XX0;
case DB_78200_ID:
return SYSMAP_DB_78200;
case DB_632X_ID:
return SYSMAP_DB_623X;
case RD_78XX0_AMC_ID:
return SYSMAP_RD_78XX0_AMC;
case RD_78XX0_MASA_ID:
return SYSMAP_RD_78XX0_MASA;
case RD_78XX0_H3C_ID:
return SYSMAP_RD_78XX0_H3C;
default:
printk("ERROR: can't find system address map\n");
return NULL;
}
}
static int do_sar_write(int argc, char *const argv[])
{
const char *cmd = argv[0];
MV_U32 temp, boardId = mvBoardIdGet();
MV_BOOL flag = MV_ERROR;
MV_U8 writeVal = simple_strtoul(argv[1], NULL, 10);
MV_FREQ_MODE cpuFreqMode;
if (boardId != DB_6660_ID && boardId != DB_6650_ID) {
printf("\nError: S@R fields are readable only for current board\n");
return 1;
}
if (argc < 2)
goto usage;
if (strcmp(cmd, "freq") == 0) {
if (mvCtrlFreqModeGet(writeVal, &cpuFreqMode) != MV_OK)
goto input_error;
else if (GetAndVerifySatr(MV_SATR_CPU_DDR_L2_FREQ, &temp) == MV_OK )
flag = mvCtrlSatRWrite(MV_SATR_CPU_DDR_L2_FREQ, writeVal, MV_FALSE);
}
else if (strcmp(cmd, "coreclock") == 0) {
if (writeVal != 0 && writeVal != 1)
goto input_error;
else if (GetAndVerifySatr(MV_SATR_CORE_CLK_SELECT, &temp) == MV_OK )
flag = mvCtrlSatRWrite(MV_SATR_CORE_CLK_SELECT, writeVal, MV_FALSE);
}
else if (strcmp(cmd, "cpusnum") == 0) {
if (writeVal != 0 && writeVal != 1)
goto input_error;
else if (GetAndVerifySatr(MV_SATR_CPU1_ENABLE, &temp) == MV_OK )
flag = mvCtrlSatRWrite(MV_SATR_CPU1_ENABLE, writeVal, MV_FALSE);
}
else if (strcmp(cmd, "sscg") == 0) {
if (writeVal != 0 && writeVal != 1)
goto input_error;
else if (GetAndVerifySatr(MV_SATR_SSCG_DISABLE, &temp) == MV_OK )
flag = mvCtrlSatRWrite(MV_SATR_SSCG_DISABLE, writeVal, MV_FALSE);
} else if (strcmp(cmd, "pcimode0") == 0) {
if (writeVal != 0 && writeVal != 1)
goto input_error;
else if (GetAndVerifySatr(MV_SATR_PEX0_CLOCK, &temp) == MV_OK)
flag = mvCtrlSatRWrite(MV_SATR_PEX0_CLOCK, writeVal, MV_FALSE);
} else if (strcmp(cmd, "pcimode1") == 0) {
if (writeVal != 0 && writeVal != 1)
goto input_error;
else if (GetAndVerifySatr(MV_SATR_PEX1_CLOCK, &temp) == MV_OK)
flag = mvCtrlSatRWrite(MV_SATR_PEX1_CLOCK, writeVal, MV_FALSE);
}
else
goto usage;
if (flag == MV_ERROR) {
printf("Write S@R failed!\n");
return 1;
}
return 0;
input_error:
printf("\nError: value is not valid for \"%s\" (%d)\n\n", cmd , writeVal);
do_sar_list(1, argv);
return 1;
usage:
printf("Usage: SatR write [options] (see help) \n");
return 1;
}
static int do_bootm_netbsd (int flag, int argc, char *argv[],
bootm_headers_t *images)
{
void (*loader)(bd_t *, image_header_t *, char *, char *);
image_header_t *os_hdr, *hdr;
ulong kernel_data, kernel_len;
char *consdev;
#ifdef CONFIG_MARVELL
DECLARE_NETBSD_CMDLINE;
bd_t *bd = gd->bd;
#else
char *cmdline;
#endif /*CONFIG_MARVELL*/
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
#if defined(CONFIG_FIT)
if (!images->legacy_hdr_valid) {
fit_unsupported_reset ("NetBSD");
return 1;
}
#endif /*defined(CONFIG_FIT)*/
hdr = images->legacy_hdr_os;
/*
* Booting a (NetBSD) kernel image
*
* This process is pretty similar to a standalone application:
* The (first part of an multi-) image must be a stage-2 loader,
* which in turn is responsible for loading & invoking the actual
* kernel. The only differences are the parameters being passed:
* besides the board info strucure, the loader expects a command
* line, the name of the console device, and (optionally) the
* address of the original image header.
*/
os_hdr = NULL;
if (image_check_type (&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) {
image_multi_getimg (hdr, 1, &kernel_data, &kernel_len);
if (kernel_len)
os_hdr = hdr;
}
consdev = "";
#if defined (CONFIG_8xx_CONS_SMC1)
consdev = "smc1";
#elif defined (CONFIG_8xx_CONS_SMC2)
consdev = "smc2";
#elif defined (CONFIG_8xx_CONS_SCC2)
consdev = "scc2";
#elif defined (CONFIG_8xx_CONS_SCC3)
consdev = "scc3";
#endif
if (argc > 2) {
ulong len;
int i;
#ifdef CONFIG_MARVELL
unsigned int mvBoardIdGet(void);
char buf[30];
sprintf(extraBootArgs ,"boardId=%x",mvBoardIdGet());
for (i = 0; i < 4; i++)
{
sprintf(buf ," dram%d_start=%lx",i, bd->bi_dram[i].start);
strcat(extraBootArgs, buf);
sprintf(buf ," dram%d_size=%lx",i, bd->bi_dram[i].size);
strcat(extraBootArgs, buf);
}
#endif /*CONFIG_MARVELL*/
for (i = 2, len = 0; i < argc; i += 1)
len += strlen (argv[i]) + 1;
#ifdef CONFIG_MARVELL
/* Adding BoardId */
len += strlen(extraBootArgs) + 1;
#endif /*CONFIG_MARVELL*/
cmdline = malloc (len);
for (i = 2, len = 0; i < argc; i += 1) {
if (i > 2)
cmdline[len++] = ' ';
strcpy ((char*)(&cmdline[len]), argv[i]);
len += strlen (argv[i]);
}
#ifdef CONFIG_MARVELL
/* Adding BoardId */
if (i > 2) cmdline[len++] = ' ';
strcpy ((char*)(&cmdline[len]), extraBootArgs);
len += strlen (extraBootArgs);
#endif /*CONFIG_MARVELL*/
} else if ((cmdline = getenv ("bootargs")) == NULL) {
cmdline = "";
}
loader = (void (*)(bd_t *, image_header_t *, char *, char *))images->ep;
printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n",
(ulong)loader);
show_boot_progress (15);
/*
* NetBSD Stage-2 Loader Parameters:
* r3: ptr to board info data
* r4: image address
* r5: console device
* r6: boot args string
*/
(*loader) (gd->bd, os_hdr, consdev, (char*)cmdline);
return 1;
}
/***********************************************************
* Init the PHY or Switch of the board *
***********************************************************/
MV_VOID mvEgigaPhySwitchInit(void)
{
if (RD_88F6183_AP == mvBoardIdGet())
{
mvEthE6161SwitchBasicInit(0);
}
else if ((DB_88F5181_5281_DDR2 == mvBoardIdGet())||
(DB_88F5X81_DDR1 == mvBoardIdGet()) ||
(DB_88F5181_DDR1_PEXPCI == mvBoardIdGet()) ||
(RD_88F5181_POS_NAS == mvBoardIdGet()) ||
(DB_88F5182_DDR2 == mvBoardIdGet())||
(DB_88F5182_DDR2_A == mvBoardIdGet())||
(DB_88F5082_DDR2 == mvBoardIdGet())||
(RD_88F5182_2XSATA == mvBoardIdGet())||
(DB_88F5181L_DDR2_2XTDM == mvBoardIdGet()) ||
(DB_88F5180N_DDR1 == mvBoardIdGet()) ||
(DB_88F5180N_DDR2 == mvBoardIdGet()) ||
(DB_88W8660_DDR2 == mvBoardIdGet()) )
{
mvEthE1111PhyBasicInit(0);
}else if ((RD_88F5182_2XSATA3 == mvBoardIdGet()) ||
(RD_88F5182_2XSATA == mvBoardIdGet()) ||
(RD_88F5082_2XSATA == mvBoardIdGet()) ||
(RD_88F5082_2XSATA3 == mvBoardIdGet()) ||
(DB_88F5X81_DDR2 == mvBoardIdGet()) ||
(RD_88F6183_GP == mvBoardIdGet()) ||
(DB_88F6183_BP == mvBoardIdGet()))
{
/* 1118 is identical to 1116 */
mvEthE1116PhyBasicInit(0);
}else if (DB_88F5181_5281_DDR1 == mvBoardIdGet())
{
mvEthE1011PhyBasicInit(0);
}else if ((RD_88F5181_VOIP == mvBoardIdGet()) || (RD_88F5181L_VOIP_FE == mvBoardIdGet()) ||
(RD_88F5181_GTW_FE == mvBoardIdGet()))
{
mvEthE6063SwitchBasicInit(0);
}else if ((RD_88W8660_DDR1 == mvBoardIdGet()) || (RD_88W8660_AP82S_DDR1 == mvBoardIdGet()))
{
mvEthE6065_61SwitchBasicInit(0);
}else if ( (RD_88F5181L_VOIP_GE == mvBoardIdGet()) ||
(RD_88F5181_GTW_GE == mvBoardIdGet()) ||
(RD_88F5181L_VOIP_FXO_GE == mvBoardIdGet()))
{
mvEthE6131SwitchBasicInit(0);
}else if (RD_88F6082_MICRO_DAS_NAS == mvBoardIdGet())
{
mvEthE1112PhyBasicInit(0);
}
else if ((DB_88F6082_BP == mvBoardIdGet()) ||
(DB_88F6082L_BP == mvBoardIdGet()))
{
mvEthE1112PhyBasicInit(0);
mvEthE1112PhyBasicInit(1);
}
else if (RD_88F6082_DX243_24G == mvBoardIdGet())
{
mvEthE1112PhyBasicInit(0);
mvEthE1111PhyBasicInit(1);
}
else if (RD_88F6082_NAS == mvBoardIdGet())
{
/* Power down phy in case we enter power down mode */
mvEthE1112PhyPowerDown(0);
mvEthE1112PhyPowerDown(1);
}
else if (RD_88F6183_AP == mvBoardIdGet())
{
mvEthE6161SwitchBasicInit(0);
}
}
/*****************************************************************************
* UART
****************************************************************************/
static struct resource mv_uart_resources[] = {
{
.start = PORT0_BASE,
.end = PORT0_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART0,
.end = IRQ_UART0,
.flags = IORESOURCE_IRQ,
},
{
.start = PORT1_BASE,
.end = PORT1_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_UART1,
.end = IRQ_UART1,
.flags = IORESOURCE_IRQ,
},
};
static struct plat_serial8250_port mv_uart_data[] = {
{
.mapbase = PORT0_BASE,
.membase = (char *)PORT0_BASE,
.irq = IRQ_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
},
{
.mapbase = PORT1_BASE,
.membase = (char *)PORT1_BASE,
.irq = IRQ_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
},
{ },
};
static struct platform_device mv_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = mv_uart_data,
},
.num_resources = ARRAY_SIZE(mv_uart_resources),
.resource = mv_uart_resources,
};
static void serial_initialize(void)
{
mv_uart_data[0].uartclk = mv_uart_data[1].uartclk = mvTclk;
platform_device_register(&mv_uart);
}
static void __init mv_vfp_init(void)
{
#if defined CONFIG_VFP_FASTVFP
printk("VFP initialized to Run Fast Mode.\n");
#endif
}
#if defined(MV_88F6183)
#ifdef CONFIG_MV_INCLUDE_AUDIO
typedef struct {
unsigned int base;
unsigned int size;
} _audio_mem_info;
typedef struct {
u32 spdif_rec;
u32 spdif_play;
u32 i2s_rec;
u32 i2s_play;
_audio_mem_info mem_array[MV_DRAM_MAX_CS + 1];
} _audio_info;
_audio_info audio_info = {1, 1, 1, 1};
static struct resource mv_snd_resources[] = {
[0] = {
.start = INTER_REGS_BASE + AUDIO_REG_BASE,
.end = INTER_REGS_BASE + AUDIO_REG_BASE + SZ_16K -1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_AUDIO_INT,
.end = IRQ_AUDIO_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = NR_IRQS, /* should obtained from board information*/
.end = NR_IRQS, /* should obtained from board information */
.flags = IORESOURCE_IRQ,
}
};
static u64 mv_snd_dmamask = 0xFFFFFFFFUL;
static struct platform_device mv_snd_device = {
.name = "mv88fx_snd",
.id = -1,
.dev = {
.dma_mask = &mv_snd_dmamask,
.coherent_dma_mask = 0xFFFFFFFF,
.platform_data = &audio_info,
},
.num_resources = ARRAY_SIZE(mv_snd_resources),
.resource = mv_snd_resources,
};
#endif /* #ifdef CONFIG_MV_INCLUDE_AUDIO */
#ifdef CONFIG_MV_INCLUDE_SDIO
static struct resource mvsdmmc_resources[] = {
[0] = {
.start = INTER_REGS_BASE + 0x80000,
.end = INTER_REGS_BASE + 0x80000 + SZ_1K -1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = SDIO_IRQ_NUM,
.end = SDIO_IRQ_NUM,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = NR_IRQS, /* should obtained from board information*/
.end = NR_IRQS, /* should obtained from board information */
.flags = IORESOURCE_IRQ,
}
};
static u64 mvsdmmc_dmamask = 0xffffffffUL;
static struct platform_device mvsdmmc_device = {
.name = "mvsdmmc",
.id = -1,
.dev = {
.dma_mask = &mvsdmmc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(mvsdmmc_resources),
.resource = mvsdmmc_resources,
};
#endif /* CONFIG_MV_INCLUDE_SDIO */
static struct platform_device *devices[] __initdata = {
#ifdef CONFIG_MV_INCLUDE_AUDIO
&mv_snd_device,
#endif
#ifdef CONFIG_MV_INCLUDE_SDIO
&mvsdmmc_device,
#endif
NULL
};
#endif /* #if defined(MV_88F6183) */
static void __init mv_init(void)
{
unsigned int temp;
/* init the Board environment */
if (mvBoardIdGet() != RD_88F6082_MICRO_DAS_NAS) /* excluded for HDD power problem - to be fixed */
mvBoardEnvInit();
/* init the controller environment */
if( mvCtrlEnvInit() ) {
printk( "Controller env initialization failed.\n" );
return;
}
if(mvBoardIdGet() == RD_88F5181_POS_NAS) {
temp = MV_REG_READ(GPP_DATA_OUT_REG(0));
temp &= ~(1 << 0x5);
/* for host mode should be set to 0 */
if(!mvIsUsbHost) {
temp |= (1 << 0x5);
}
MV_REG_WRITE(GPP_DATA_OUT_REG(0), temp);
}
/* Init the CPU windows setting and the access protection windows. */
if( mvCpuIfInit(mv_sys_map()) ) {
printk( "Cpu Interface initialization failed.\n" );
return;
}
/* Init Tclk & SysClk */
mvTclk = mvBoardTclkGet();
mvSysclk = mvBoardSysClkGet();
printk("Sys Clk = %d, Tclk = %d\n",mvSysclk ,mvTclk );
if ((mvCtrlModelGet() == MV_5281_DEV_ID) || (mvCtrlModelGet() == MV_1281_DEV_ID)
|| (mvCtrlModelGet() == MV_6183_DEV_ID))
mv_orion_ver = MV_ORION2; /* Orion II */
else
mv_orion_ver = MV_ORION1; /* Orion I */
/* Implement workaround for FEr# CPU-C16: Wait for interrupt command */
/* is not processed properly, the workaround is not to use this command */
/* the erratum is relevant for 5281 devices with revision less than C0 */
if((mvCtrlModelGet() == MV_5281_DEV_ID)
&& (mvCtrlRevGet() < MV_5281_C0_REV))
{
support_wait_for_interrupt = 0;
}
#ifdef CONFIG_JTAG_DEBUG
support_wait_for_interrupt = 0; /* for Lauterbach */
#endif
mv_vfp_init();
elf_hwcap &= ~HWCAP_JAVA;
serial_initialize();
/* At this point, the CPU windows are configured according to default definitions in mvSysHwConfig.h */
/* and cpuAddrWinMap table in mvCpuIf.c. Now it's time to change defaults for each platform. */
mvCpuIfAddDecShow();
#if defined(CONFIG_MTD_PHYSMAP)
mv_mtd_initialize();
#endif
print_board_info();
#ifdef CONFIG_MV_INCLUDE_IDMA
mvDmaInit();
#endif
#if defined(MV_88F6183)
#ifdef CONFIG_MV_INCLUDE_SDIO
mvsdmmc_resources[2].end = mvBoardSDIOGpioPinGet() + IRQ_GPP_START;
mvsdmmc_resources[2].start = mvBoardSDIOGpioPinGet() + IRQ_GPP_START;
irq_int_type[mvBoardSDIOGpioPinGet()] = GPP_IRQ_TYPE_CHANGE_LEVEL;
#endif /* CONFIG_MV_INCLUDE_SDIO */
#ifdef CONFIG_MV_INCLUDE_AUDIO
for (temp=0 ; temp< MV_DRAM_MAX_CS; temp++) {
MV_DRAM_DEC_WIN win;
audio_info.mem_array[temp].base = 0;
audio_info.mem_array[temp].size = 0;
mvDramIfWinGet(SDRAM_CS0 + temp, &win);
if (win.enable) {
audio_info.mem_array[temp].base = win.addrWin.baseLow;
audio_info.mem_array[temp].size = win.addrWin.size;
}
}
#endif /* CONFIG_MV_INCLUDE_AUDIO */
if ((temp = ARRAY_SIZE(devices) - 1))
platform_add_devices(devices, temp);
#endif /* MV_88F6183 */
return;
}
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor;
unsigned int i;
MV_GPP_HAL_DATA gppHalData;
clock_divisor = (CONFIG_SYS_TCLK / 16)/115200;
/* muti-core support, initiate each Uart to each cpu */
mvUartInit(whoAmI(), clock_divisor, mvUartBase(whoAmI()));
if (whoAmI() != 0)
return 0;
#if defined(MV_INCLUDE_TWSI)
MV_TWSI_ADDR slave;
#endif
maskAllInt();
/* must initialize the int in order for udelay to work */
/* interrupt_init(); - no interrupt handling in u-boot */
timer_init();
/* Init the Board environment module (device bank params init) */
mvBoardEnvInit();
#if defined(MV_INCLUDE_TWSI)
slave.type = ADDR7_BIT;
slave.address = 0;
mvTwsiInit(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_TCLK, &slave, 0);
#endif
/* Init the Controlloer environment module (MPP init) */
mvCtrlEnvInit();
#if defined(CONFIG_DISPLAY_CPUINFO)
late_print_cpuinfo(); /* display cpu info (and speed) */
#endif
mvBoardDebugLed(2);
/* Init the Controller CPU interface */
mvCpuIfInit(mvCpuAddrWinMap);
#if defined(MV_NOR_BOOT)
env_init();
#endif
if (mvBoardCpssBoardIdSet(mvBoardIdGet()) != MV_OK)
printf("%s: Error: Failed to set Board ID for CPSS!\n", __func__);
/* Init the GPIO sub-system */
gppHalData.ctrlRev = mvCtrlRevGet();
mvGppInit(&gppHalData);
/* arch number of Integrator Board */
gd->bd->bi_arch_number=mv_get_arch_number();
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
/* relocate the exception vectors */
/* U-Boot is running from DRAM at this stage */
for(i = 0; i < 0x100; i+=4) {
*(unsigned int *)(0x0 + i) = *(unsigned int*)(CONFIG_SYS_TEXT_BASE + i);
}
mvBoardDebugLed(4);
return 0;
}
/*******************************************************************************
* mvCtrlHighSpeedSerdesPhyConfig
*
* DESCRIPTION: This is the main function which configure the
* PU sequence of the ser-des
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK - success
* MV_ERROR - failure
*******************************************************************************/
MV_STATUS mvCtrlHighSpeedSerdesPhyConfig(MV_VOID)
{
MV_U32 serdesLaneNum, pexUnit;
MV_U32 uiReg;
MV_BIN_SERDES_UNIT_INDX serdesLaneCfg;
MV_U32 regAddr[16][11], regVal[16][11]; /* addr/value for each line @ every setup step */
MV_U8 maxSerdesLanes;
MV_U32 tmp;
MV_U32 tempReg, tempPexReg;
MV_U32 pexIf=0;
MV_U32 first_busno, next_busno;
MV_U32 addr;
MV_TWSI_ADDR slave;
MV_U32 boardId = mvBoardIdIndexGet(mvBoardIdGet());
maxSerdesLanes = mvCtrlSerdesMaxLanesGet();
if (maxSerdesLanes == 0)
return MV_OK;
/*Set MPP1 for twsi access */
uiReg = (MV_REG_READ(MPP_CONTROL_REG(1)) & 0x00FFFFFF) | 0x22000000;
MV_REG_WRITE(MPP_CONTROL_REG(1), uiReg);
/* TWSI init */
slave.type = ADDR7_BIT;
slave.address = 0;
mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0);
mvUartInit();
/* update board configuration (serdes lane topology and speed), if needed */
mvBoardUpdateBoardTopologyConfig(boardId);
/* Initialize board configuration database */
boardLaneConfig[0] = SERDES_UNIT_PEX; /* SerDes 0 is alwyas PCIe0*/
boardLaneConfig[1] = boardTopologyConfig[boardId].serdesTopology.lane1;
boardLaneConfig[2] = boardTopologyConfig[boardId].serdesTopology.lane2;
boardLaneConfig[3] = boardTopologyConfig[boardId].serdesTopology.lane3;
memset(regAddr, 0, sizeof(regAddr));
memset(regVal, 0, sizeof(regVal));
/* Check if DRAM is already initialized */
if (MV_REG_READ(REG_BOOTROM_ROUTINE_ADDR) & (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
DEBUG_INIT_S("High speed PHY - Version: ");
DEBUG_INIT_S(SERDES_VERION);
DEBUG_INIT_S(" - 2nd boot - Skip \n");
return MV_OK;
}
DEBUG_INIT_S("High speed PHY - Version: ");
DEBUG_INIT_S(SERDES_VERION);
DEBUG_INIT_S(" (COM-PHY-V20) \n");
DEBUG_INIT_FULL_C("SERDES 0=",boardLaneConfig[0],2);
DEBUG_INIT_FULL_C("SERDES 1=",boardLaneConfig[1],2);
DEBUG_INIT_FULL_C("SERDES 2=",boardLaneConfig[2],2);
DEBUG_INIT_FULL_C("SERDES 3=",boardLaneConfig[3],2);
/*------------------------------------------*/
/* STEP - 1.5 Power Down PLL, RX, TX all phys */
/*------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++)
{
uiReg=MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum));
uiReg &= ~PIN_TX_IDLE_MASK;
uiReg &= ~(PHY_POWER_UP_PLL_MASK | PHY_POWER_UP_RX_MASK | PHY_POWER_UP_TX_MASK);
MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg);
}
mvOsUDelay(10000);
/*--------------------------------------------------------*/
/* STEP - 2 Reset PHY and PIPE (Zx: Un-reset, Ax: Reset)*/
/*--------------------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++)
{
#ifndef CONFIG_ALP_A375_ZX_REV
resetPhyAndPipe(serdesLaneNum, MV_TRUE);
#else
resetPhyAndPipe(serdesLaneNum, MV_FALSE);
#endif
}
/*--------------------------------*/
/* STEP - 2 Common PHYs Selectors */
/*--------------------------------*/
MV_REG_WRITE(COMMON_PHY_SELECTOR_REG, GetLaneSelectorConfig());
/*--------------------------------*/
/* STEP - 3 Configuration 1 */
/*--------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum);
if(serdesLaneCfg >= SERDES_LAST_UNIT){
return MV_ERROR;
}
uiReg = MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum));
switch(serdesLaneCfg){
case SERDES_UNIT_USB3:
#ifndef CONFIG_ALP_A375_ZX_REV
A375_A0_COMMON_PHY_CONFIG(uiReg);
#endif
uiReg |= PHY_MODE_MASK; /* PHY Mode = USB */
uiReg |= PIPE_SELECT_MASK ; /* Select USB3_PEX */
break;
case SERDES_UNIT_PEX:
uiReg |= PIPE_SELECT_MASK ; /* Select USB3_PEX */
#ifndef CONFIG_ALP_A375_ZX_REV
uiReg &= ~(PHY_MODE_MASK); /* PHY Mode = PEX */
A375_A0_COMMON_PHY_CONFIG(uiReg);
#endif
break;
case SERDES_UNIT_SGMII:
case SERDES_UNIT_SATA:
#ifndef CONFIG_ALP_A375_ZX_REV
A375_A0_COMMON_PHY_CONFIG(uiReg);
#endif
uiReg &= ~(PIPE_SELECT_MASK); /* Select SATA_SGMII */
uiReg |= POWER_UP_IVREF_MASK; /* Power UP IVREF = Power Up */
break;
case SERDES_UNIT_UNCONNECTED:
default:
break;
}
/* Serdes speed config */
tmp = getSerdesSpeedConfig(boardId, serdesLaneCfg);
uiReg &= ~(GEN_RX_MASK); /* SERDES RX Speed config */
uiReg |= tmp<<GEN_RX_OFFS;
uiReg &= ~(GEN_TX_MASK); /* SERDES TX Speed config */
uiReg |= tmp<<GEN_TX_OFFS;
MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg);
}
#ifndef CONFIG_ALP_A375_ZX_REV
/*------------------------------------------*/
/* STEP - 3.5 Unreset PHY and PIPE(only Ax)*/
/*------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
resetPhyAndPipe(serdesLaneNum, MV_FALSE);
}
#endif
/*----------------------------------------*/
/* STEP - 4 COMPHY register configuration */
/*----------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum);
if(serdesLaneCfg >= SERDES_LAST_UNIT){
return MV_ERROR;
}
switch(serdesLaneCfg){
case SERDES_UNIT_PEX:
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x25); /* Enable soft_reset*/
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC60); /* PHY Mode = PEX */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6017); /* REFCLK SEL =0x0 (100Mhz) */
MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(KVCO_CALOBRATION_CONTROL_REG(serdesLaneNum),0x40); /* use_max_pll_rate=0x0, ext_force_cal_done=0x0 */
#endif
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x24); /* Release soft_reset */
break;
case SERDES_UNIT_USB3:
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x21); /* Enable soft_reset*/
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFCA0); /* PHY Mode = USB3 */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(LANE_CONFIGURATION_4_REG(serdesLaneNum),0x13); /* Ref_Clk =100Mhz */
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6017); /* REFCLK SEL =0x0 (100Mhz) */
MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(KVCO_CALOBRATION_CONTROL_REG(serdesLaneNum),0x40); /* use_max_pll_rate=0x0, ext_force_cal_done=0x0 */
MV_REG_WRITE(GENERETION_2_SETTINGS_1_REG(serdesLaneNum),0x149); /* Mulitiple frequency setup */
#endif
MV_REG_WRITE(RESET_AND_CLOCK_CONTROL_REG(serdesLaneNum),0x20); /* Release soft_reset */
break;
case SERDES_UNIT_SATA:
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC01); /* PHY Mode = SATA */
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6417); /* REFCLK SEL =0x1 (25Mhz) */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(INTERFACE_REG1_REG(serdesLaneNum),0x1400); /* PHY_Gen_Max = 5G */
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x400); /* SEL_Bits = 20-Bit */
MV_REG_WRITE(DIGITAL_RESERVED0_REG(serdesLaneNum),0xE); /* Reg_sq_de_glitch_en */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(RESERVED_46_REG(serdesLaneNum),0xFF00);
#endif
break;
case SERDES_UNIT_SGMII:
MV_REG_WRITE(POWER_AND_PLL_CONTROL_REG(serdesLaneNum),0xFC81); /* PHY Mode = SGMII */ /*moti need to change offset*/
MV_REG_WRITE(DIGITAL_LOOPBACK_ENABLE_REG(serdesLaneNum),0x0); /* SEL_BITS = 0x0 (10-bits mode) */
MV_REG_WRITE(MISCELLANEOUS_CONTROL0_REG(serdesLaneNum),0x6417); /* REFCLK SEL =0x1 (25Mhz) */
#ifndef CONFIG_ALP_A375_ZX_REV
MV_REG_WRITE(DIGITAL_RESERVED0_REG(serdesLaneNum),0xE); /* Reg_sq_de_glitch_en */
A375_A0_RESET_DFE_SEQUENCE(serdesLaneNum);
#else
MV_REG_WRITE(RESERVED_46_REG(serdesLaneNum),0xFF00); /* Enable soft_reset*/
#endif
MV_REG_WRITE(PHY_ISOLATION_MODE_CONTROL_REG(serdesLaneNum),0x166); /* Set PHY_GEN_TX/RX to 1.25Gbps */
break;
case SERDES_UNIT_UNCONNECTED:
default:
break;
}
}
/*------------------------------------------*/
/* STEP - 4.5 Power up PLL, RX, TX all phys */
/*------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++)
{
uiReg=MV_REG_READ(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum));
uiReg |= (PHY_POWER_UP_PLL_MASK | PHY_POWER_UP_RX_MASK | PHY_POWER_UP_TX_MASK);
MV_REG_WRITE(COMMON_PHY_CONFIGURATION1_REG(serdesLaneNum),uiReg);
}
#ifndef CONFIG_ALP_A375_ZX_REV
mvOsUDelay(5000);
/*--------------------------------------------------------------------*/
/* STEP - 4.6 (Only SGMII/SATA): WAIT for PHY Power up sequence to finish */
/*--------------------------------------------------------------------*/
for (serdesLaneNum = 0; serdesLaneNum < maxSerdesLanes; serdesLaneNum++) {
serdesLaneCfg = mvGetSerdesLaneCfg(serdesLaneNum);
if(serdesLaneCfg >= SERDES_LAST_UNIT){
return MV_ERROR;
}
switch(serdesLaneCfg){
case SERDES_UNIT_SATA:
case SERDES_UNIT_SGMII:
uiReg = MV_REG_READ(COMMON_PHY_STATUS1_REG(serdesLaneNum));
if ((uiReg & 0x6) != 0x6) {
DEBUG_INIT_S("Phy Power up did't finished\n");
return MV_ERROR;
}
case SERDES_UNIT_UNCONNECTED:
default:
break;
}
}
#endif
/*----------------------------------------*/
/* STEP - 5 PEX Only */
/*----------------------------------------*/
for (pexUnit = 0; pexUnit < 4; pexUnit++) {
if (boardLaneConfig[pexUnit] != SERDES_UNIT_PEX)
continue;
tmp = MV_REG_READ(PEX_CAPABILITIES_REG(pexUnit));
DEBUG_RD_REG(PEX_CAPABILITIES_REG(pexUnit), tmp );
tmp &= ~(0xf<<20);
tmp |= (0x4<<20);
MV_REG_WRITE(PEX_CAPABILITIES_REG(pexUnit),tmp);
DEBUG_WR_REG(PEX_CAPABILITIES_REG(pexUnit),tmp);
}
tmp = MV_REG_READ(SOC_CTRL_REG);
DEBUG_RD_REG(SOC_CTRL_REG, tmp);
tmp &= ~(0x03);
tmp |= 0x1<<PCIE0_ENABLE_OFFS;
if (boardLaneConfig[1] == SERDES_UNIT_PEX)
tmp |= 0x1<<PCIE1_ENABLE_OFFS;
MV_REG_WRITE(SOC_CTRL_REG, tmp);
DEBUG_WR_REG(SOC_CTRL_REG, tmp);
/*----------------------------------------*/
/* STEP - 6 PEX Only - support gen1/gen2 */
/*----------------------------------------*/
next_busno = 0;
mvOsDelay(150);
for (pexIf = 0; pexIf < 2; pexIf++) // only pexIf 0 on
{
if (boardLaneConfig[pexIf] != SERDES_UNIT_PEX)
continue;
tmp = MV_REG_READ(PEX_DBG_STATUS_REG(pexIf));
DEBUG_RD_REG(PEX_DBG_STATUS_REG(pexIf), tmp);
first_busno = next_busno;
if ((tmp & 0x7f) == 0x7E) {
next_busno++;
tempPexReg = MV_REG_READ((PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CAPABILITY_REG)));
DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CAPABILITY_REG)),tempPexReg );
tempPexReg &= (0xF);
if (tempPexReg == 0x2) {
tempReg = (MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) & 0xF0000) >> 16;
DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG),tempReg );
/* check if the link established is GEN1 */
if (tempReg == 0x1) {
mvPexLocalBusNumSet(pexIf, first_busno);
mvPexLocalDevNumSet(pexIf, 1);
DEBUG_INIT_FULL_S("PEX: pexIf ");
DEBUG_INIT_FULL_D(pexIf, 1);
DEBUG_INIT_FULL_S(", link is Gen1, checking the EP capability \n");
/* link is Gen1, check the EP capability */
addr = mvPexConfigRead(pexIf, first_busno, 0, 0, 0x34) & 0xFF;
DEBUG_INIT_FULL_C("mvPexConfigRead: return addr=0x%x", addr,4);
if (addr == 0xff) {
DEBUG_INIT_FULL_C("mvPexConfigRead: return 0xff -->PEX (%d): Detected No Link.", pexIf,1);
continue;
}
while ((mvPexConfigRead(pexIf, first_busno, 0, 0, addr) & 0xFF) != 0x10) {
addr = (mvPexConfigRead(pexIf, first_busno, 0, 0, addr) & 0xFF00) >> 8;
}
if ((mvPexConfigRead(pexIf, first_busno, 0, 0, addr + 0xC) & 0xF) >= 0x2) {
tmp = MV_REG_READ(PEX_LINK_CTRL_STATUS2_REG(pexIf));
DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp );
tmp &=~(BIT0 | BIT1);
tmp |= BIT1;
MV_REG_WRITE(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp);
DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pexIf),tmp);
tmp = MV_REG_READ(PEX_CTRL_REG(pexIf));
DEBUG_RD_REG(PEX_CTRL_REG(pexIf), tmp );
tmp |= BIT10;
MV_REG_WRITE(PEX_CTRL_REG(pexIf),tmp);
DEBUG_WR_REG(PEX_CTRL_REG(pexIf),tmp);
mvOsUDelay(10000);/* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state*/
DEBUG_INIT_FULL_S("PEX: pexIf ");
DEBUG_INIT_FULL_D(pexIf, 1);
DEBUG_INIT_FULL_S(", Link upgraded to Gen2 based on client cpabilities \n");
} else {
DEBUG_INIT_FULL_S("PEX: pexIf ");
DEBUG_INIT_FULL_D(pexIf, 1);
DEBUG_INIT_FULL_S(", remains Gen1\n");
}
}
}
static MV_STATUS pciDetectDevice(MV_U32 pciIf,
MV_U32 bus,
MV_U32 dev,
MV_U32 func,
MV_PCI_DEVICE *pPciAgent)
{
MV_U32 pciData;
/* no Parameters checking ! because it is static function and it is assumed
that all parameters were checked in the calling function */
/* Try read the PCI Vendor ID and Device ID */
/* We will scan only ourselves and the PCI slots that exist on the
board, because we may have a case that we have one slot that has
a Cardbus connector, and because CardBus answers all IDsels we want
to scan only this slot and ourseleves.
*/
#if defined(MV_INCLUDE_PCI)
if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) &&
(DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) &&
(DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) &&
(DB_88F5181_DDR1_MNG != mvBoardIdGet()))
{
if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE)
{
return MV_ERROR;
}
}
#endif /* defined(MV_INCLUDE_PCI) */
pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID);
if (PCI_ERROR_CODE == pciData)
{
/* no device exist */
return MV_ERROR;
}
/* we are here ! means a device is detected */
/* fill basic information */
pPciAgent->busNumber=bus;
pPciAgent->deviceNum=dev;
pPciAgent->function=func;
/* Fill the PCI Vendor ID and Device ID */
pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS;
pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS;
/* Read Status and command */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
PCI_STATUS_AND_COMMAND);
/* Fill related Status and Command information*/
if (pciData & PSCR_TAR_FAST_BB)
{
pPciAgent->isFastB2BCapable = MV_TRUE;
}
else
{
pPciAgent->isFastB2BCapable = MV_FALSE;
}
if (pciData & PSCR_CAP_LIST)
{
pPciAgent->isCapListSupport=MV_TRUE;
}
else
{
pPciAgent->isCapListSupport=MV_FALSE;
}
if (pciData & PSCR_66MHZ_EN)
{
pPciAgent->is66MHZCapable=MV_TRUE;
}
else
{
pPciAgent->is66MHZCapable=MV_FALSE;
}
/* Read Class Code and Revision */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
PCI_CLASS_CODE_AND_REVISION_ID);
pPciAgent->baseClassCode =
(pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS;
pPciAgent->subClassCode =
(pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS;
pPciAgent->progIf =
(pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS;
pPciAgent->revisionID =
(pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
/* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE);
pPciAgent->pciCacheLine=
(pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS;
pPciAgent->pciLatencyTimer=
(pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS;
switch (pciData & PBHTLTCLR_HEADER_MASK)
{
case PBHTLTCLR_HEADER_STANDARD:
pPciAgent->pciHeader=MV_PCI_STANDARD;
break;
case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE:
pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE;
break;
}
if (pciData & PBHTLTCLR_MULTI_FUNC)
{
pPciAgent->isMultiFunction=MV_TRUE;
}
else
{
pPciAgent->isMultiFunction=MV_FALSE;
}
if (pciData & PBHTLTCLR_BISTCAP)
{
pPciAgent->isBISTCapable=MV_TRUE;
}
else
{
pPciAgent->isBISTCapable=MV_FALSE;
}
/* read this device pci bars */
pciDetectDeviceBars(pciIf,
bus,dev,func,
pPciAgent);
/* check if we are bridge*/
if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&&
(pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE))
{
/* Read P2P_BUSSES_NUM */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
P2P_BUSSES_NUM);
pPciAgent->p2pPrimBusNum =
(pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS;
pPciAgent->p2pSecBusNum =
(pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS;
pPciAgent->p2pSubBusNum =
(pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS;
pPciAgent->p2pSecLatencyTimer =
(pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS;
/* Read P2P_IO_BASE_LIMIT_SEC_STATUS */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
P2P_IO_BASE_LIMIT_SEC_STATUS);
pPciAgent->p2pSecStatus =
(pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS;
pPciAgent->p2pIObase =
(pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS;
/* clear low address (should be zero)*/
pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK;
pPciAgent->p2pIOLimit =
(pciData & PIBLSS_IO_LIMIT_MASK);
/* fill low address with 0xfff */
pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK;
switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS)
{
case PIBLSS_ADD_CAP_16BIT:
pPciAgent->bIO32 = MV_FALSE;
break;
case PIBLSS_ADD_CAP_32BIT:
pPciAgent->bIO32 = MV_TRUE;
/* Read P2P_IO_BASE_LIMIT_UPPER_16 */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
P2P_IO_BASE_LIMIT_UPPER_16);
pPciAgent->p2pIObase |=
(pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS;
pPciAgent->p2pIOLimit |=
(pciData & PRBU_IO_UPP_LIMIT_MASK);
break;
}
/* Read P2P_MEM_BASE_LIMIT */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
P2P_MEM_BASE_LIMIT);
pPciAgent->p2pMemBase =
(pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS;
/* clear low address */
pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK;
pPciAgent->p2pMemLimit =
(pciData & PMBL_MEM_LIMIT_MASK);
/* add 0xfffff */
pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK;
/* Read P2P_PREF_MEM_BASE_LIMIT */
pciData = mvPciIfConfigRead(pciIf,
bus,dev,func,
P2P_PREF_MEM_BASE_LIMIT);
pPciAgent->p2pPrefMemBase =
(pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS;
/* get high address only */
pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK;
pPciAgent->p2pPrefMemLimit =
(pciData & PRMBL_PREF_MEM_LIMIT_MASK);
/* add 0xfffff */
pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK;
switch (pciData & PRMBL_ADD_CAP_MASK)
{
case PRMBL_ADD_CAP_32BIT:
pPciAgent->bPrefMem64 = MV_FALSE;
/* Read P2P_PREF_BASE_UPPER_32 */
pPciAgent->p2pPrefBaseUpper32Bits = 0;
/* Read P2P_PREF_LIMIT_UPPER_32 */
pPciAgent->p2pPrefLimitUpper32Bits = 0;
break;
case PRMBL_ADD_CAP_64BIT:
pPciAgent->bPrefMem64 = MV_TRUE;
/* Read P2P_PREF_BASE_UPPER_32 */
pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf,
bus,dev,func,
P2P_PREF_BASE_UPPER_32);
/* Read P2P_PREF_LIMIT_UPPER_32 */
pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf,
bus,dev,func,
P2P_PREF_LIMIT_UPPER_32);
break;
}
}
