/******************************************************************************* * mvSysEthPhyInit - Initialize the EthPhy subsystem * * DESCRIPTION: * * INPUT: * None * OUTPUT: * None * RETURN: * None * *******************************************************************************/ MV_STATUS mvSysEthPhyInit(void) { MV_ETHPHY_HAL_DATA halData; MV_U32 port; for (port=0; port < mvCtrlEthMaxPortGet(); port++) { halData.phyAddr[port] = mvBoardPhyAddrGet(port); halData.LinkCryptPortAddr[port] = mvBoardPhyLinkCryptPortAddrGet(port); halData.boardSpecInit = MV_FALSE; halData.isSgmii[port] = mvBoardIsPortInSgmii(port); halData.QuadPhyPort0[port] = mvBoardQuadPhyAddr0Get(port); } halData.ethPhySmiReg = ETH_SMI_REG(MV_ETH_SMI_PORT); return mvEthPhyHalInit(&halData); }
/******************************************************************************* * mvSysEthInit - Initialize the Eth subsystem * * DESCRIPTION: * * INPUT: * None * OUTPUT: * None * RETURN: * None * *******************************************************************************/ MV_VOID mvSysEthInit(MV_VOID) { MV_ETH_HAL_DATA halData; MV_U32 port; MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1]; MV_STATUS status; int i; status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1); if (status != MV_OK) return; for (i = 0; i < MAX_TARGETS; i++) { if (addrWinMap[i].enable == MV_FALSE) continue; } halData.maxPortNum = mvCtrlEthMaxPortGet(); halData.cpuPclk = mvCpuPclkGet(); halData.tclk = mvBoardTclkGet(); #ifdef ETH_DESCR_IN_SRAM halData.sramSize = mvCtrlSramSizeGet(); #endif for (port = 0; port < halData.maxPortNum; port++) { if (MV_FALSE == mvBoardIsGbEPortConnected(port)) continue; if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) { halData.portData[port].powerOn = MV_FALSE; continue; } status = mvEthWinInit(port, addrWinMap); if (status == MV_OK) { halData.portData[port].powerOn = MV_TRUE; halData.portData[port].phyAddr = mvBoardPhyAddrGet(port); halData.portData[port].isSgmii = mvBoardIsPortInSgmii(port); halData.portData[port].macSpeed = mvBoardMacSpeedGet(port); } } mvEthHalInit(&halData); return; }
static int mvEgigaInit(struct eth_device *dev, bd_t *p) { egigaPriv *priv = dev->priv; MV_STATUS status; int i, phys_queue, phys_port; MV_BOARD_MAC_SPEED mac_speed; MV_ETH_PORT_SPEED speed = 0; MV_32 phy_addr; static MV_U8 mac_bcast[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; mv_eth_bm_start(); /* init each port only once */ if (priv->devInit != MV_TRUE) { /* port power up - release from reset */ if (!MV_PP2_IS_PON_PORT(priv->port)) { phy_addr = mvBoardPhyAddrGet(priv->port); if (phy_addr != -1) { mvGmacPhyAddrSet(priv->port, phy_addr); mvEthPhyInit(priv->port, MV_FALSE); } mvGmacPortPowerUp(priv->port, mvBoardIsPortInSgmii(priv->port), MV_FALSE/*mvBoardIsPortInRgmii(priv->port)*/); } /* init the hal -- create internal port control structure and descriptor rings, */ /* open address decode windows, disable rx and tx operations. mask interrupts. */ priv->halPriv = mvPp2PortInit(priv->port, priv->port * CONFIG_MV_ETH_RXQ, CONFIG_MV_ETH_RXQ, NULL); if (!priv->halPriv) { printf("falied to init eth port (error)\n"); goto error; } /* after init port - init rx & tx */ MV_PP2_PHYS_RXQ_CTRL *rxqCtrl = mvPp2RxqInit(priv->port, EGIGA_DEF_RXQ, EGIGA_RXQ_LEN); if (!rxqCtrl) { printf("Rxq Init Failed\n"); goto error; } MV_PP2_PHYS_TXQ_CTRL *txqCtrl = mvPp2TxqInit(priv->port, EGIGA_DEF_TXP, EGIGA_DEF_TXQ, EGIGA_TXQ_LEN, EGIGA_TXQ_HWF_LEN); if (!txqCtrl) { printf("Txq Init Failed\n"); goto error; } mvPp2RxqBmLongPoolSet(priv->port, EGIGA_DEF_RXQ, EGIGA_BM_POOL); mvPp2RxqBmShortPoolSet(priv->port, EGIGA_DEF_RXQ, EGIGA_BM_POOL); mvPp2RxqNonOccupDescAdd(priv->port, EGIGA_DEF_RXQ, EGIGA_RXQ_LEN); mvPp2TxpMaxTxSizeSet(priv->port, EGIGA_DEF_TXP, RX_PKT_SIZE); priv->devInit = MV_TRUE; } mac_speed = mvBoardMacSpeedGet(priv->port); if (mac_speed != BOARD_MAC_SPEED_AUTO) { switch (mac_speed) { case BOARD_MAC_SPEED_10M: speed = MV_ETH_SPEED_10; break; case BOARD_MAC_SPEED_100M: speed = MV_ETH_SPEED_100; break; case BOARD_MAC_SPEED_1000M: case BOARD_MAC_SPEED_2000M: speed = MV_ETH_SPEED_1000; break; default: /* do nothing */ break; } if (mvGmacForceLinkModeSet(priv->port, MV_TRUE, MV_FALSE)) { printf("mvEthForceLinkModeSet failed\n"); goto error; } if (mvGmacSpeedDuplexSet(priv->port, speed, MV_ETH_DUPLEX_FULL)) { printf("mvEthSpeedDuplexSet failed\n"); goto error; } if (mvGmacFlowCtrlSet(priv->port, MV_ETH_FC_DISABLE)) { printf("mvEthFlowCtrlSet failed\n"); goto error; } } /* allow new packets to RXQs */ mvPp2PortIngressEnable(priv->port, 1); /* classifier port default config */ phys_queue = mvPp2LogicRxqToPhysRxq(priv->port, EGIGA_DEF_RXQ); phys_port = MV_PPV2_PORT_PHYS(priv->port); mvPp2ClsHwPortDefConfig(phys_port, 0, FLOWID_DEF(phys_port), phys_queue); if (mvPrsMacDaAccept(phys_port, mac_bcast, 1 /*add*/)) { printf("%s: mvPrsMacDaAccept failed\n", dev->name); return -1; } if (mvPrsMacDaAccept(phys_port, dev->enetaddr, 1 /*add*/)) { printf("%s: mvPrsMacDaAccept failed\n", dev->name); return -1; } if (mvPrsDefFlow(phys_port)) { printf("%s: mvPp2PrsDefFlow failed\n", dev->name); return -1; } /* start the hal - rx/tx activity */ /* Check if link is up for 2 Sec */ for (i = 1; i < 100; i++) { status = mvPp2PortEnable(priv->port, 1); if (status == MV_OK) { priv->devEnable = MV_TRUE; break; } mvOsDelay(20); } if (status != MV_OK) { printf("%s: %s mvPp2PortEnable failed (error)\n", __func__, dev->name); goto error; } mvPp2PortEgressEnable(priv->port, 1); return 1; error: if (priv->devInit) mvEgigaHalt(dev); printf("%s: %s failed\n", __func__, dev->name); return -1; }