static int __init
cesadev_init(void)
{
int rc;
if (mvCtrlPwrClckGet(CESA_UNIT_ID, 0) == MV_FALSE)
return 0;
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA))
{
dprintk("CESA is not mapped to this CPU\n");
return -ENODEV;
}
#endif
if(mvUnitMapIsMine(CESA) == MV_FALSE)
return -ENODEV;
#ifdef CONFIG_MV_CESA_TEST
cesaTestStart(buf_num, buf_size);
#endif
dprintk("%s(%p)\n", __FUNCTION__, cesadev_init);
rc = misc_register(&cesadev);
if (rc) {
printk(KERN_ERR "cesadev: registration of /dev/cesadev failed\n");
return(rc);
}
return(0);
}
void mvEthAddrDecShow(void)
{
int port;
for(port=0; port<mvCtrlEthMaxPortGet(); port++)
{
if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port)) continue;
mvEthPortAddrDecShow(port);
}
}
MV_VOID mvAudioAddrDecShow(MV_VOID)
{
int unit;
for (unit = 0; unit < MV_AUDIO_MAX_UNITS; unit++)
{
if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, unit)) continue;
mvAudioUnitAddrDecShow(unit);
}
}
void mvEthInit(void)
{
MV_U32 port;
/* Power down all existing ports */
for(port=0; port<mvCtrlEthMaxPortGet(); port++)
{
if (MV_FALSE == mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port)) continue;
mvEthWinInit(port);
}
mvEthHalInit();
}
/*******************************************************************************
* mvCpuIfEnablePex - Enable PCI Express.
*
* DESCRIPTION:
* This function enables PCI Express access to the device address
* space.
*
* INPUT:
* pexIf - The PCI-E interface to enable.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvCpuIfEnablePex(MV_U32 pexIf)
{
MV_U32 reg;
if (mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf) == MV_TRUE) {
if (pexIf == 0) {
reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0, PEX_LINK_CAPABILITY_REG));
reg &= ~PXLC_MAX_LNK_SPEED_MASK;
reg |= (0x1 << PXLC_MAX_LNK_SPEED_OFFS);
MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(0, PEX_LINK_CAPABILITY_REG), reg);
}
/* CPU config register Pex enable */
MV_REG_BIT_SET(CPU_CTRL_STAT_REG, CCSR_PCI_ACCESS_MASK(pexIf));
}
}
/*******************************************************************************
* mvSysEthInit - Initialize the Eth subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_VOID mvSysEthInit(MV_VOID)
{
MV_ETH_HAL_DATA halData;
MV_U32 port;
MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1];
MV_STATUS status;
int i;
status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1);
if (status != MV_OK)
return;
for (i = 0; i < MAX_TARGETS; i++) {
if (addrWinMap[i].enable == MV_FALSE)
continue;
}
halData.maxPortNum = mvCtrlEthMaxPortGet();
halData.cpuPclk = mvCpuPclkGet();
halData.tclk = mvBoardTclkGet();
#ifdef ETH_DESCR_IN_SRAM
halData.sramSize = mvCtrlSramSizeGet();
#endif
for (port = 0; port < halData.maxPortNum; port++) {
if (MV_FALSE == mvBoardIsGbEPortConnected(port)) continue;
if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE) {
halData.portData[port].powerOn = MV_FALSE;
continue;
}
status = mvEthWinInit(port, addrWinMap);
if (status == MV_OK) {
halData.portData[port].powerOn = MV_TRUE;
halData.portData[port].phyAddr = mvBoardPhyAddrGet(port);
halData.portData[port].isSgmii = mvBoardIsPortInSgmii(port);
halData.portData[port].macSpeed = mvBoardMacSpeedGet(port);
}
}
mvEthHalInit(&halData);
return;
}
/***********************************************************
* mv_eth_initialize -- *
* main driver initialization. loading the interfaces. *
***********************************************************/
int mv_eth_initialize(bd_t *bis)
{
int port;
MV_8 *enet_addr;
MV_8 name[NAMESIZE+1];
MV_8 enetvar[9];
/* HAL init + port power up + port win init */
mvSysPp2Init();
mv_eth_bm_init();
/* Parser default initialization */
if (mvPrsDefaultInit())
printf("Warning PARSER default init failed\n");
if (mvPp2ClassifierDefInit())
printf("Warning Classifier defauld init failed\n");
if (mvPp2AggrTxqInit(0/*cpu*/, EGIGA_TXQ_LEN) == NULL) {
printf("Error failed to init aggr TXQ\n");
return -1;
}
for (port = 0; port < mvCtrlEthMaxPortGet(); port++) {
if (MV_PP2_IS_PON_PORT(port) || mvBoardIsPortLoopback(port))
continue;
if (mvBoardIsEthActive(port) == MV_FALSE)
continue;
if (mvCtrlPwrClckGet(ETH_GIG_UNIT_ID, port) == MV_FALSE)
continue;
/* interface name */
sprintf(name, "egiga%d", port);
/* interface MAC addr extract */
sprintf(enetvar, port ? "eth%daddr" : "ethaddr", port);
enet_addr = getenv(enetvar);
mvEgigaLoad(port, name, enet_addr);
}
return 0;
}
/*******************************************************************************
* mvSataAddrDecShow - Print the SATA address decode map.
*
* DESCRIPTION:
* This function print the SATA address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
MV_VOID mvSataAddrDecShow(MV_VOID)
{
MV_SATA_DEC_WIN win;
int i,j;
for( j = 0; j < MV_SATA_MAX_CHAN; j++ )
{
if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j))
return;
mvOsOutput( "\n" );
mvOsOutput( "SATA %d:\n", j );
mvOsOutput( "----\n" );
for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ )
{
memset( &win, 0, sizeof(MV_SATA_DEC_WIN) );
mvOsOutput( "win%d - ", i );
if( mvSataWinGet(j, i, &win ) == MV_OK )
{
if( win.enable )
{
mvOsOutput( "%s base %08x, ",
mvCtrlTargetNameGet(win.target), win.addrWin.baseLow );
mvOsOutput( "...." );
mvSizePrint( win.addrWin.size );
mvOsOutput( "\n" );
}
else
mvOsOutput( "disable\n" );
}
}
}
}
int mv_usb_resume(int dev)
{
int status, isHost;
char *name_ptr;
if (MV_FALSE == mvCtrlPwrClckGet(USB_UNIT_ID, dev)) {
printk(KERN_DEBUG "\nWarning Integrated USB %d is Powered Off\n", dev);
return -EINVAL;
}
/* Check if this USB is mapped to this AMP group - YY */
if(MV_FALSE == mvUnitMapIsMine(USB0 + dev))
return -EINVAL;
isHost = mvIsUsbHost & (1 << dev);
name_ptr = isHost ? usb_host_name : usb_dev_name;
printk(KERN_DEBUG "registered dev#%d as a %s\n", dev, name_ptr);
status = mvSysUsbInit(dev, isHost);
return status;
}
/*******************************************************************************
* mvSysPexInit - Initialize the Pex subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_STATUS mvSysPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType)
{
MV_PEX_HAL_DATA halData;
MV_UNIT_WIN_INFO addrWinMap[MAX_TARGETS + 1];
MV_STATUS status;
if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf))
return MV_ERROR;
status = mvCtrlAddrWinMapBuild(addrWinMap, MAX_TARGETS + 1);
if (status == MV_OK)
status = mvPexWinInit(pexIf, pexType, addrWinMap);
if (status == MV_OK) {
halData.ctrlModel = mvCtrlModelGet();
halData.maxPexIf = mvCtrlPexMaxIfGet();
halData.ctrlFamily=mvCtrlDevFamilyIdGet(halData.ctrlModel);
status = mvPexInit(pexIf, pexType, &halData);
}
return status;
}
/*******************************************************************************
* mvTsuAddrDecShow
*
* DESCRIPTION:
* Print the TSU address decode map.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* None.
*
*******************************************************************************/
void mvTsuAddrDecShow(void)
{
MV_TSU_DEC_WIN win;
int i;
if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0))
return;
mvOsOutput( "\n" );
mvOsOutput( "TSU:\n");
mvOsOutput( "----\n" );
for(i = 0; i < TSU_MAX_DECODE_WIN; i++)
{
memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN));
mvOsOutput( "win%d - ", i );
if(mvTsuWinGet(i, &win ) == MV_OK )
{
if(win.enable == MV_TRUE)
{
mvOsOutput("%s base %08x, ",
mvCtrlTargetNameGet(win.target),
win.addrWin.baseLow);
mvOsOutput( "...." );
mvSizePrint(win.addrWin.size );
mvOsOutput( "\n" );
}
else
{
mvOsOutput( "disable\n" );
}
}
}
return;
}
int cesa_init(void)
{
u8 chan = 0;
int i;
const char *irq_str[] = {"cesa0", "cesa1"};
printk(KERN_INFO "in %s\n", __func__);
for (i = 0; i < 2; i++)
spin_lock_init(&cesa_lock[i]);
if (mvCtrlPwrClckGet(CESA_UNIT_ID, 0) == MV_FALSE)
return 0;
if (MV_OK != my_mvSysCesaInit(1, 256, NULL)) {
printk(KERN_INFO "%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__);
return EINVAL;
}
/* clear and unmask Int */
MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG(chan), 0);
MV_REG_WRITE(MV_CESA_ISR_MASK_REG(chan), MV_CESA_CAUSE_ACC_DMA_MASK);
if (request_irq(CESA_IRQ(0), nfp_sec_interrupt_handler_0,
(IRQF_DISABLED) , irq_str[chan], NULL)) {
printk(KERN_INFO "%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, CESA_IRQ(chan));
return EINVAL;
}
chan = 1;
MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG(chan), 0);
MV_REG_WRITE(MV_CESA_ISR_MASK_REG(chan), MV_CESA_CAUSE_ACC_DMA_MASK);
if (request_irq(CESA_IRQ(1), nfp_sec_interrupt_handler_1,
(IRQF_DISABLED) , irq_str[chan], NULL)) {
printk(KERN_INFO "%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, CESA_IRQ(chan));
return EINVAL;
}
atomic_set(&req_count[0], 0);
atomic_set(&req_count[1], 0);
mvOsPrintf("MV_CESA_TDMA_CTRL_REG address 0 %08x\n\n", MV_CESA_TDMA_CTRL_REG(0));
mvOsPrintf("MV_CESA_TDMA_CTRL_REG address 1 %08x\n\n", MV_CESA_TDMA_CTRL_REG(1));
mvOsPrintf("MV_CESA_TDMA_CTRL_REG(0) %08x\n",
MV_REG_READ(MV_CESA_TDMA_CTRL_REG(0)));
mvOsPrintf("MV_CESA_TDMA_CTRL_REG(1) %08x\n",
MV_REG_READ(MV_CESA_TDMA_CTRL_REG(1)));
memset(&sa, 0, sizeof(MV_NFP_SEC_SA_ENTRY));
sa.digestSize = MV_CESA_SHA1_DIGEST_SIZE;
sa.ivSize = MV_CESA_AES_BLOCK_SIZE;
sa.spi = 3;
sa.tunProt = MV_NFP_SEC_TUNNEL;
sa.encap = MV_NFP_SEC_ESP;
sa.seqNum = 4;
sa.tunnelHdr.sIp = 0x6400A8C0;
sa.tunnelHdr.dIp = 0x6401A8C0;
sa.tunnelHdr.outIfIndex = 0;
sa.lifeTime = 0;
sa.secOp = MV_NFP_SEC_ENCRYPT;
strcpy(sa.tunnelHdr.dstMac, "aabbccddeeff");
strcpy(sa.tunnelHdr.srcMac, "abacadaeafaa");
return 0;
}
static int __init mv_usb_init(void)
{
int status, dev, num, isHost;
char* name_ptr;
struct platform_device* mv_usb_dev_ptr;
num = mvCtrlUsbMaxGet();
for(dev=0; dev<num; dev++)
{
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
if (MV_FALSE == mvSocUnitIsMappedToThisCpu(USB0+dev))
{
printk(KERN_INFO"USB %d is not mapped to this CPU\n", dev);
continue;
}
#endif
if (MV_FALSE == mvCtrlPwrClckGet(USB_UNIT_ID, dev))
{
printk("\nWarning Integrated USB %d is Powered Off\n",dev);
continue;
}
isHost = mvIsUsbHost & (1 << dev);
if(isHost)
{
name_ptr = usb_host_name;
}
else
{
name_ptr = usb_dev_name;
}
status = mvUsbInit(dev, isHost);
mv_usb_dev_ptr = kmalloc(sizeof(struct platform_device), GFP_KERNEL);
if(mv_usb_dev_ptr == NULL)
{
printk("Can't allocate platform_device structure - %d bytes\n",
sizeof(struct platform_device) );
return 1;
}
memset(mv_usb_dev_ptr, 0, sizeof(struct platform_device) );
mv_usb_dev_ptr->name = name_ptr;
mv_usb_dev_ptr->id = PCI_VENDOR_ID_MARVELL | (MV_USB_VERSION << 16) | (dev << 24);
mv_usb_dev_ptr->num_resources = 2;
mv_usb_dev_ptr->resource = (struct resource*)kmalloc(2*sizeof(struct resource), GFP_KERNEL);
if(mv_usb_dev_ptr->resource == NULL)
{
printk("Can't allocate 2 resource structure - %d bytes\n",
2*sizeof(struct resource) );
return 1;
}
memset(mv_usb_dev_ptr->resource, 0, 2*sizeof(struct resource));
mv_usb_dev_ptr->resource[0].start =
( INTER_REGS_BASE | MV_USB_CORE_CAP_LENGTH_REG(dev));
mv_usb_dev_ptr->resource[0].end =
((INTER_REGS_BASE | MV_USB_CORE_CAP_LENGTH_REG(dev)) + 4096);
mv_usb_dev_ptr->resource[0].flags = IORESOURCE_DMA;
mv_usb_dev_ptr->resource[1].start = IRQ_USB_CTRL(dev);
mv_usb_dev_ptr->resource[1].flags = IORESOURCE_IRQ;
mv_usb_dev_ptr->dev.dma_mask = kmalloc(sizeof(u64), GFP_KERNEL);
*mv_usb_dev_ptr->dev.dma_mask = MV_USB_DMA_MASK;
mv_usb_dev_ptr->dev.coherent_dma_mask = ~0;
mv_usb_dev_ptr->dev.release = mv_usb_release;
strncpy(mv_usb_dev_ptr->dev.bus_id, usb_bus_name, BUS_ID_SIZE);
printk("Marvell USB EHCI %s controller #%d: %p\n",
isHost ? "Host" : "Gadget", dev, mv_usb_dev_ptr);
status = platform_device_register(mv_usb_dev_ptr);
if (status)
{
printk("Can't register Marvell USB EHCI controller #%d, status=%d\n",
dev, status);
return status;
}
}
return 0;
}
/*
* Initialize the TSU driver
*/
int mvtsu_init(void)
{
int result, i;
dev_t dev;
TSU_ENTER(TSU_DBG_INIT, "mvtsu_init");
/* Check unit power mode. */
if(mvCtrlPwrClckGet(TS_UNIT_ID,0) == MV_FALSE) {
printk("Warning: TS unit is powered off.\n");
TSU_LEAVE(TSU_DBG_INIT, "mvtsu_init");
return 0;
}
/* Parse command line parameters. */
mvtsu_parse_cmdline();
dev = MKDEV(MV_TSU_MAJOR, 0);
result = register_chrdev_region(dev, TSU_NUM_DEVICES, TSU_DEV_NAME);
if (result < 0) {
printk("Failed to register char device (%d,%d)\n",result, TSU_NUM_DEVICES);
TSU_LEAVE(TSU_DBG_INIT, "mvtsu_init");
return result;
}
/* Perform unit initialization. */
result = mvSysTsuInit(cfg_core_clk, cfg_tsu_mode ,NULL);
if(result != MV_OK) {
goto fail_init;
result = -EINVAL;
}
TSU_DPRINT(TSU_DBG_INIT, ("\tTSU unit initialized successfully.\n"));
/* Create the char device. */
for (i = 0; i < TSU_NUM_DEVICES; i++) {
mvtsu_devs[i].port = i;
mvtsu_set_defaults(&mvtsu_devs[i]);
cdev_init(&mvtsu_devs[i].cdev, &mvtsu_fops);
mvtsu_devs[i].cdev.owner = THIS_MODULE;
mvtsu_devs[i].cdev.ops = &mvtsu_fops;
dev = MKDEV(MV_TSU_MAJOR, i);
result = cdev_add (&mvtsu_devs[i].cdev, dev, 1);
if (result) {
printk(KERN_ERR "Error %d adding tsu%d", result, i);
goto fail_add;
}
spin_lock_init(&mvtsu_devs[i].lock);
TSU_DPRINT(TSU_DBG_INIT, ("\tChar device %d initialized.\n",i));
}
#ifdef CONFIG_MV_TSU_PROC
TSU_DPRINT(TSU_DBG_INIT, ("\tCreating Proc entry.\n"));
mvtsu_proc_init();
#endif /* CONFIG_MV_TSU_PROC */
printk("Transport Stream interface registered.\n");
printk(" o %s Mode.\n",
(cfg_tsu_mode == TSU_MODE_PARALLEL) ? "Parallel" : "Serial");
printk(" o Core-Clock - ");
switch (cfg_core_clk) {
case (TSU_CORE_CLK_83_MHZ):
printk("83");
break;
case (TSU_CORE_CLK_71_MHZ):
printk("71");
break;
case (TSU_CORE_CLK_91_MHZ):
printk("91");
break;
case (TSU_CORE_CLK_100_MHZ):
printk("100");
break;
}
printk(" MHz.\n");
printk(" o Packet Size - %d Bytes.\n",cfg_pkt_size);
TSU_LEAVE(TSU_DBG_INIT, "mvtsu_init");
return 0;
fail_add:
while(i > 0) {
cdev_del(&mvtsu_devs[i-1].cdev);
i--;
}
fail_init:
dev = MKDEV(MV_TSU_MAJOR, 0);
unregister_chrdev_region(dev, TSU_NUM_DEVICES);
TSU_LEAVE(TSU_DBG_INIT, "mvtsu_init");
return result;
}
/*
* our driver startup and shutdown routines
*/
static int
mv_cesa_ocf_init(struct platform_device *pdev)
{
#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X)
if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA))
{
dprintk("CESA is not mapped to this CPU\n");
return -ENODEV;
}
#endif
dprintk("%s\n", __FUNCTION__);
memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev));
softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods);
cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE);
if (cesa_ocf_id < 0)
panic("MV CESA crypto device cannot initialize!");
dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id);
/* CESA unit is auto power on off */
#if 0
if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0))
{
printk("\nWarning CESA %d is Powered Off\n",0);
return EINVAL;
}
#endif
memset(&cesa_device, 0, sizeof(struct cesa_dev));
/* Get the IRQ, and crypto memory regions */
{
struct resource *res;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
if (!res)
return -ENXIO;
cesa_device.sram = ioremap(res->start, res->end - res->start + 1);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
if (!res) {
iounmap(cesa_device.sram);
return -ENXIO;
}
cesa_device.reg = ioremap(res->start, res->end - res->start + 1);
cesa_device.irq = platform_get_irq(pdev, 0);
cesa_device.plat_data = pdev->dev.platform_data;
setup_tdma_mbus_windows(&cesa_device);
}
if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg,
NULL) ) {
printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__);
return EINVAL;
}
/* clear and unmask Int */
MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0);
#ifndef CESA_OCF_POLLING
MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK);
#endif
#ifdef CESA_OCF_TASKLET
tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0);
#endif
/* register interrupt */
if( request_irq( cesa_device.irq, cesa_interrupt_handler,
(IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) {
printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg);
return EINVAL;
}
memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES);
#define REGISTER(alg) \
crypto_register(cesa_ocf_id, alg, 0,0)
REGISTER(CRYPTO_AES_CBC);
REGISTER(CRYPTO_DES_CBC);
REGISTER(CRYPTO_3DES_CBC);
REGISTER(CRYPTO_MD5);
REGISTER(CRYPTO_MD5_HMAC);
REGISTER(CRYPTO_SHA1);
REGISTER(CRYPTO_SHA1_HMAC);
#undef REGISTER
return 0;
}
static int __init mv_usb_init(void)
{
int status, dev, num, isHost;
char* name_ptr;
struct platform_device* mv_usb_dev_ptr;
int irq_num[3] = { IRQ_AURORA_USB0,
IRQ_AURORA_USB1,
IRQ_AURORA_USB2};
num = mvCtrlUsbMaxGet();
if (num > MAX_USB_PORTS) {
printk("WARNING: Limited USB ports number to %d\n", MAX_USB_PORTS);
num = MAX_USB_PORTS;
}
for(dev=0; dev<num; dev++)
{
if (MV_FALSE == mvCtrlPwrClckGet(USB_UNIT_ID, dev))
{
printk("\nWarning Integrated USB %d is Powered Off\n",dev);
continue;
}
/* Check if this USB is mapped to this AMP group - YY */
if(MV_FALSE == mvUnitMapIsMine(USB0 + dev))
{
continue;
}
isHost = mvIsUsbHost & (1 << dev);
if(isHost)
name_ptr = usb_host_name;
else
name_ptr = usb_dev_name;
printk("registered dev#%d asa %s\n",dev,name_ptr);
status = mvSysUsbInit(dev, isHost);
mv_usb_dev_ptr = kmalloc(sizeof(struct platform_device), GFP_KERNEL);
if(mv_usb_dev_ptr == NULL)
{
printk("Can't allocate platform_device structure - %d bytes\n",
sizeof(struct platform_device) );
return 1;
}
memset(mv_usb_dev_ptr, 0, sizeof(struct platform_device) );
mv_usb_dev_ptr->name = name_ptr;
mv_usb_dev_ptr->id = dev;
mv_usb_dev_ptr->num_resources = 2;
mv_usb_dev_ptr->resource = (struct resource*)kmalloc(2*sizeof(struct resource), GFP_KERNEL);
if(mv_usb_dev_ptr->resource == NULL)
{
printk("Can't allocate 2 resource structure - %d bytes\n",
2*sizeof(struct resource) );
kfree(mv_usb_dev_ptr);
return 1;
}
memset(mv_usb_dev_ptr->resource, 0, 2*sizeof(struct resource));
mv_usb_dev_ptr->resource[0].start =
( INTER_REGS_BASE | MV_USB_CORE_CAP_LENGTH_REG(dev));
mv_usb_dev_ptr->resource[0].end =
((INTER_REGS_BASE | MV_USB_CORE_CAP_LENGTH_REG(dev)) + 4096);
mv_usb_dev_ptr->resource[0].flags = IORESOURCE_DMA;
mv_usb_dev_ptr->resource[1].start = irq_num[dev];
mv_usb_dev_ptr->resource[1].flags = IORESOURCE_IRQ;
mv_usb_dev_ptr->dev.dma_mask = kmalloc(sizeof(u64), GFP_KERNEL);
*mv_usb_dev_ptr->dev.dma_mask = MV_USB_DMA_MASK;
mv_usb_dev_ptr->dev.coherent_dma_mask = ~0;
mv_usb_dev_ptr->dev.release = mv_usb_release;
dev_set_name(&mv_usb_dev_ptr->dev, "%s", usb_bus_name);
printk("Marvell USB %s controller #%d: %p\n",
isHost ? "EHCI Host" : "Gadget", dev, mv_usb_dev_ptr);
status = platform_device_register(mv_usb_dev_ptr);
if (status)
{
printk("Can't register Marvell USB EHCI controller #%d, status=%d\n",
dev, status);
return status;
}
}
return 0;
}
int mvtsu_open (struct inode *inode, struct file *filp)
{
struct mvtsu_dev *dev;
MV_TSU_PORT_CONFIG port_cfg;
MV_TSU_BUFF_INFO *binfo = NULL;
MV_STATUS status;
int result = 0;
int stat_size = 0;
int data_size = 0;
int data_buff_offs;
TSU_ENTER(TSU_DBG_OPEN, "mvtsu_open");
if(MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) {
printk("Transport Stream interface is powered off.\n");
return 0;
}
/* Find the device structure. */
dev = container_of(inode->i_cdev, struct mvtsu_dev, cdev);
/* Determine the port direction according to the read / write flag.*/
if ((filp->f_mode & (FMODE_WRITE | FMODE_READ)) == FMODE_WRITE) {
port_cfg.portDir = TSU_PORT_OUTPUT;
} else if ((filp->f_mode & (FMODE_WRITE | FMODE_READ)) == FMODE_READ) {
port_cfg.portDir = TSU_PORT_INPUT;
} else {
result = -EINVAL;
goto fail_init;
}
/* Reset the port. */
mvTsuPortReset(dev->port);
/* Initialize the port. */
port_cfg.pktSize = cfg_pkt_size;
status = mvTsuPortInit(dev->port,&port_cfg);
if(status != MV_OK) {
result = -EINVAL;
goto fail_init;
}
TSU_DPRINT(TSU_DBG_OPEN, ("\tTSU unit initialized successfully.\n"));
/* Initialize the port buffers. */
binfo = &dev->buff_info;
switch(binfo->aggrMode)
{
case (MV_TSU_AGGR_MODE_DISABLED):
binfo->dataBlockSize = port_cfg.pktSize;
dev->valid_data_size = port_cfg.pktSize;
dev->rd_rw_data_size = binfo->dataBlockSize + TSU_DONE_STATUS_ENTRY_SIZE;
binfo->aggrNumPackets = 1;
break;
case (MV_TSU_AGGR_MODE_1):
binfo->dataBlockSize = port_cfg.pktSize * binfo->aggrNumPackets;
if(port_cfg.portDir == TSU_PORT_OUTPUT) {
binfo->dataBlockSize += MV_MAX(TSU_DMA_ALIGN,TSU_MODE1_OUT_TMS_SIZE);
dev->rd_rw_data_size = binfo->dataBlockSize;
}
else {
dev->rd_rw_data_size = binfo->dataBlockSize +
(binfo->aggrNumPackets * TSU_DONE_STATUS_ENTRY_SIZE);
}
dev->valid_data_size = port_cfg.pktSize * binfo->aggrNumPackets;
break;
case (MV_TSU_AGGR_MODE_2):
binfo->aggrMode2TmstmpOff = TSU_DMA_ALIGN -
(port_cfg.pktSize & (TSU_DMA_ALIGN - 1));
binfo->dataBlockSize =
(binfo->aggrNumPackets *
(port_cfg.pktSize + binfo->aggrMode2TmstmpOff) +
TSU_DMA_ALIGN);
dev->valid_data_size = (binfo->aggrNumPackets *
(port_cfg.pktSize + binfo->aggrMode2TmstmpOff));
dev->rd_rw_data_size = dev->valid_data_size;
default:
break;
}
dev->port_dir = port_cfg.portDir;
/* Align the data block size to a cache line. */
binfo->dataBlockSize = MV_ALIGN_UP(binfo->dataBlockSize,32);
data_size = binfo->dataBlockSize * binfo->numTsDesc;
#ifdef TSU_UNCACHED_DATA_BUFFERS
binfo->tsDataBuff =
mvOsIoUncachedMalloc(NULL,data_size,(MV_ULONG*)(&binfo->tsDataBuffPhys),
NULL);
#else
binfo->tsDataBuff =
mvOsIoCachedMalloc(NULL,data_size,(MV_ULONG*)(&binfo->tsDataBuffPhys),
NULL);
#endif /* TSU_UNCACHED_DATA_BUFFERS */
if(binfo->tsDataBuff == NULL) {
result = -ENOMEM;
goto fail_init;
}
// memset(binfo->tsDataBuff,0x88,data_size);
#ifndef TSU_UNCACHED_DATA_BUFFERS
mvOsCacheClear(NULL,(MV_U32*)TSU_DATA_BUFF_HW_2_SW(binfo->tsDataBuff),
data_size);
#endif /* TSU_UNCACHED_DATA_BUFFERS */
/* Align tsDataBuff according to the HW limitation. */
if(binfo->aggrMode == MV_TSU_AGGR_MODE_2) {
data_buff_offs = port_cfg.pktSize & (TSU_DMA_ALIGN - 1);
}
else if((binfo->aggrMode == MV_TSU_AGGR_MODE_1) &&
(port_cfg.portDir == TSU_PORT_OUTPUT)) {
data_buff_offs = TSU_DMA_ALIGN - TSU_MODE1_OUT_TMS_SIZE;
}
else {
data_buff_offs = 0;
}
binfo->tsDataBuff = (MV_U32*)((MV_U32)binfo->tsDataBuff + data_buff_offs);
binfo->tsDataBuffPhys += data_buff_offs;
TSU_DPRINT(TSU_DBG_OPEN, ("\tTSU Data buffer allocated successfully "
"(%p, %d).\n",binfo->tsDataBuff, data_size));
/* Allocate memory for done queue. */
stat_size = TSU_DONE_STATUS_ENTRY_SIZE * binfo->numDoneQEntry;
dev->stat_buff_size = stat_size;
binfo->tsDoneBuff =
mvOsIoUncachedMalloc(NULL,stat_size,
(MV_ULONG*)(&binfo->tsDoneBuffPhys),NULL);
if(binfo->tsDoneBuff == NULL) {
result = -ENOMEM;
goto fail_init;
}
TSU_DPRINT(TSU_DBG_OPEN, ("\tTSU Done buffer allocated successfully"
"(%p, %d).\n",binfo->tsDoneBuff, stat_size));
status = mvTsuBuffersInit(dev->port,&dev->buff_info);
if(status != MV_OK) {
TSU_DPRINT(TSU_DBG_OPEN, ("\tmvTsuBuffersInit() Failed (%d).",
status));
result = -EINVAL;
goto fail_init;
}
TSU_DPRINT(TSU_DBG_OPEN, ("\tHAL Buffers initialized successfully.\n"));
status = mvTsuPortSignalCfgSet(dev->port,&(dev->signal_cfg),dev->serial_sig_flags);
if(status != MV_OK) {
TSU_DPRINT(TSU_DBG_OPEN, ("\tmvTsuPortSignalCfgSet() Failed (%d).",
status));
result = -EINVAL;
goto fail_init;
}
TSU_DPRINT(TSU_DBG_OPEN, ("\tPort signal parameters set successfully.\n"));
status = mvTsuRxSyncDetectionSet(dev->port,dev->sync_detect,dev->sync_loss);
if(status != MV_OK) {
TSU_DPRINT(TSU_DBG_OPEN, ("\tmvTsuRxSyncDetectionSet() Failed (%d).",
status));
result = -EINVAL;
goto fail_init;
}
TSU_DPRINT(TSU_DBG_OPEN, ("\tRx sync parameters set successfully.\n"));
mvtsu_rd_wr_timeout_calc(dev);
if(dev->port_dir == TSU_PORT_OUTPUT) {
mvtsu_tx_timestamp_calc(dev);
}
/* Register IRQ. */
MV_REG_WRITE(MV_TSU_INTERRUPT_MASK_REG(dev->port),TSU_DFLT_INT_MASK);
if(request_irq(IRQ_TS_INT(dev->port),mvtsu_interrupt_handler,
IRQF_DISABLED | IRQF_SAMPLE_RANDOM,"tsu",dev)) {
printk(KERN_ERR "Cannot assign irq%d to TSU port%d\n",
IRQ_TS_INT(dev->port), dev->port);
goto fail_init;
}
TSU_DPRINT(TSU_DBG_OPEN, ("\tTSU interrupt registered at IRQ %d.\n",
IRQ_TS_INT(dev->port)));
if(port_cfg.portDir == TSU_PORT_INPUT) {
/* Enable Rx timestamp. */
mvTsuRxTimestampCntEn(dev->port,MV_TRUE);
mvTsuDmaWatermarkSet(dev->port,0x8);
}
/* Make the private_data hold the pointer to the device data. */
filp->private_data = dev;
TSU_LEAVE(TSU_DBG_OPEN, "mvtsu_open");
return 0;
fail_init:
if(binfo != NULL) {
if(binfo->tsDataBuff != NULL)
#ifdef TSU_UNCACHED_DATA_BUFFERS
mvOsIoUncachedFree(
NULL,data_size,
TSU_DATA_BUFF_HW_2_SW(binfo->tsDataBuffPhys),
(MV_U32*)TSU_DATA_BUFF_HW_2_SW(binfo->tsDataBuff),0);
#else
mvOsIoCachedFree(
NULL,data_size,
TSU_DATA_BUFF_HW_2_SW(binfo->tsDataBuffPhys),
(MV_U32*)TSU_DATA_BUFF_HW_2_SW(binfo->tsDataBuff),0);
#endif /* TSU_UNCACHED_DATA_BUFFERS */
if(binfo->tsDoneBuff != NULL)
mvOsIoUncachedFree(NULL,stat_size,binfo->tsDoneBuffPhys,
binfo->tsDoneBuff,0);
binfo->tsDataBuff = NULL;
binfo->tsDoneBuff = NULL;
}
TSU_LEAVE(TSU_DBG_OPEN, "mvtsu_open");
return result;
}
MV_STATUS tdm_if_init(tdm_if_register_ops_t* register_ops, tdm_if_params_t* tdm_if_params)
{
MV_TDM_PARAMS tdm_params;
printk("Loading Marvell Telephony Driver\n");
/* Check if any SLIC module exists */
if(mvBoardTdmDevicesCountGet() == 0) {
mvCtrlPwrClckSet(TDM_2CH_UNIT_ID, 0, MV_FALSE);
printk("%s: Warning, no SLIC module is connected\n",__FUNCTION__);
return MV_OK;
}
/* Check that selected TDM unit is active */
if (MV_FALSE == mvCtrlPwrClckGet(mvCtrlTdmUnitTypeGet(), 0)) {
printk("%s: Warning, TDM is powered off\n",__FUNCTION__);
return MV_OK;
}
if((register_ops == NULL) || (tdm_if_params == NULL)) {
printk("%s: bad parameters\n",__FUNCTION__);
return MV_ERROR;
}
/* Check callbacks */
if(register_ops->tdm_if_pcm_ops.pcm_tx_callback == NULL ||
register_ops->tdm_if_pcm_ops.pcm_rx_callback == NULL ) {
printk("%s: missing parameters\n",__FUNCTION__);
return MV_ERROR;
}
/* Reset globals */
rxBuff = txBuff = NULL;
#ifdef CONFIG_MV_TDM_SUPPORT
pcm_enable = 0;
#else
pcm_enable = 1;
#endif
irq_init = 0;
tdm_init = 0;
/* Extract test enable */
test_enable = tdm_if_params->test_enable;
/* Calculate Rx/Tx buffer size(use in callbacks) */
buff_size = (tdm_if_params->pcm_format * tdm_if_params->total_lines * 80 *
(tdm_if_params->sampling_period/MV_TDM_BASE_SAMPLING_PERIOD));
/* Extract TDM irq number */
irqnr = mvCtrlTdmUnitIrqGet();
/* Start Marvell trace */
TRC_START();
TRC_INIT(NULL, NULL, 0, 0);
TRC_REC("->%s\n",__FUNCTION__);
/* Assign TDM parameters */
memcpy(&tdm_params, tdm_if_params, sizeof(MV_TDM_PARAMS));
/* Assign control callbacks */
tdm_if_register_ops = register_ops;
tdm_if_register_ops->tdm_if_ctl_ops.ctl_pcm_start = tdm_if_pcm_start;
tdm_if_register_ops->tdm_if_ctl_ops.ctl_pcm_stop = tdm_if_pcm_stop;
/* TDM init */
if(mvSysTdmInit(&tdm_params) != MV_OK) {
printk("%s: Error, TDM initialization failed !!!\n",__FUNCTION__);
return MV_ERROR;
}
tdm_init = 1;
/* Register TDM interrupt */
if (request_irq(irqnr, tdm_if_isr, IRQF_DISABLED, "tdm", NULL)) {
printk("%s: Failed to connect irq(%d)\n", __FUNCTION__, irqnr);
return MV_ERROR;
}
irq_init = 1;
/* Create TDM procFS statistics */
tdm_stats = proc_mkdir("tdm", NULL);
create_proc_read_entry("tdm_init", 0, tdm_stats, proc_tdm_init_read, NULL);
create_proc_read_entry("rx_miss", 0, tdm_stats, proc_rx_miss_read, NULL);
create_proc_read_entry("tx_miss", 0, tdm_stats, proc_tx_miss_read, NULL);
create_proc_read_entry("rx_over", 0, tdm_stats, proc_rx_over_read, NULL);
create_proc_read_entry("tx_under", 0, tdm_stats, proc_tx_under_read, NULL);
TRC_REC("Marvell Telephony Driver Loaded Successfully\n");
#ifdef CONFIG_MV_COMM_UNIT_SUPPORT
/* WA to stop the MCDMA gracefully after commUnit initialization */
tdm_if_pcm_stop();
#endif
TRC_REC("<-%s\n",__FUNCTION__);
return MV_OK;
}
