static void m53_set_clock(void) { int ret; const uint32_t ref_clk = MXC_HCLK; const uint32_t dramclk = 400; uint32_t cpuclk; imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0, PAD_CTL_DSE_HIGH | PAD_CTL_PKE)); gpio_direction_input(IMX_GPIO_NR(4, 0)); /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */ cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); if (ret) printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); if (ret) { printf("CPU: Switch peripheral clock to %dMHz failed\n", dramclk); } ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); if (ret) printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); }
static void setup_clocks(void) { int ret; u32 ref_clk = MXC_HCLK; /* * CPU clock set to 800MHz and DDR to 400MHz */ ret = mxc_set_clock(ref_clk, 800, MXC_ARM_CLK); if (ret) printf("CPU: Switch CPU clock to 800MHZ failed\n"); ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); if (ret) printf("CPU: Switch DDR clock to 400MHz failed\n"); }
static void clock_1GHz(void) { int ret; u32 ref_clk = MXC_HCLK; /* * After increasing voltage to 1.25V, we can switch * CPU clock to 1GHz and DDR to 400MHz safely */ ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); if (ret) printf("CPU: Switch CPU clock to 1GHZ failed\n"); ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); if (ret) printf("CPU: Switch DDR clock to 400MHz failed\n"); }
static void set_clock(void) { u32 ref_clk = MXC_HCLK; const uint32_t cpuclk = CPU_CLOCK; const uint32_t dramclk = 400; int ret; ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); if (ret) printf("CPU: Switch CPU clock to %dMHZ failed\n", cpuclk); ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK); if (ret) printf("CPU: Switch peripheral clock to %dMHz failed\n", dramclk); ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK); if (ret) printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk); }
static void m53_set_nand(void) { u32 i; /* NAND flash is muxed on ATA pins */ setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK); /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */ for (i = 0x4; i < 0x94; i += 0x18) { clrbits_le32(WEIM_BASE_ADDR + i, WEIM_GCR2_MUX16_BYP_GRANT_MASK); } mxc_set_clock(0, 33, MXC_NFC_CLK); enable_nfc_clk(1); }