static int __devinit myri_sbus_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
static unsigned version_printed;
struct net_device *dev;
struct myri_eth *mp;
const void *prop;
static int num;
int i, len;
DET(("myri_ether_init(%p,%d):\n", op, num));
dev = alloc_etherdev(sizeof(struct myri_eth));
if (!dev)
return -ENOMEM;
if (version_printed++ == 0)
;
SET_NETDEV_DEV(dev, &op->dev);
mp = netdev_priv(dev);
spin_lock_init(&mp->irq_lock);
mp->myri_op = op;
/* Clean out skb arrays. */
for (i = 0; i < (RX_RING_SIZE + 1); i++)
mp->rx_skbs[i] = NULL;
for (i = 0; i < TX_RING_SIZE; i++)
mp->tx_skbs[i] = NULL;
/* First check for EEPROM information. */
prop = of_get_property(dp, "myrinet-eeprom-info", &len);
if (prop)
memcpy(&mp->eeprom, prop, sizeof(struct myri_eeprom));
if (!prop) {
/* No eeprom property, must cook up the values ourselves. */
DET(("No EEPROM: "));
mp->eeprom.bus_type = BUS_TYPE_SBUS;
mp->eeprom.cpuvers =
of_getintprop_default(dp, "cpu_version", 0);
mp->eeprom.cval =
of_getintprop_default(dp, "clock_value", 0);
mp->eeprom.ramsz = of_getintprop_default(dp, "sram_size", 0);
if (!mp->eeprom.cpuvers)
mp->eeprom.cpuvers = CPUVERS_2_3;
if (mp->eeprom.cpuvers < CPUVERS_3_0)
mp->eeprom.cval = 0;
if (!mp->eeprom.ramsz)
mp->eeprom.ramsz = (128 * 1024);
prop = of_get_property(dp, "myrinet-board-id", &len);
if (prop)
memcpy(&mp->eeprom.id[0], prop, 6);
else
set_boardid_from_idprom(mp, num);
prop = of_get_property(dp, "fpga_version", &len);
if (prop)
memcpy(&mp->eeprom.fvers[0], prop, 32);
else
memset(&mp->eeprom.fvers[0], 0, 32);
if (mp->eeprom.cpuvers == CPUVERS_4_1) {
if (mp->eeprom.ramsz == (128 * 1024))
mp->eeprom.ramsz = (256 * 1024);
if ((mp->eeprom.cval == 0x40414041) ||
(mp->eeprom.cval == 0x90449044))
mp->eeprom.cval = 0x50e450e4;
}
}
#ifdef DEBUG_DETECT
dump_eeprom(mp);
#endif
for (i = 0; i < 6; i++)
dev->dev_addr[i] = mp->eeprom.id[i];
determine_reg_space_size(mp);
/* Map in the MyriCOM register/localram set. */
if (mp->eeprom.cpuvers < CPUVERS_4_0) {
/* XXX Makes no sense, if control reg is non-existent this
* XXX driver cannot function at all... maybe pre-4.0 is
* XXX only a valid version for PCI cards? Ask feldy...
*/
DET(("Mapping regs for cpuvers < CPUVERS_4_0\n"));
mp->regs = of_ioremap(&op->resource[0], 0,
mp->reg_size, "MyriCOM Regs");
if (!mp->regs) {
;
goto err;
}
mp->lanai = mp->regs + (256 * 1024);
mp->lregs = mp->lanai + (0x10000 * 2);
} else {
DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n"));
mp->cregs = of_ioremap(&op->resource[0], 0,
PAGE_SIZE, "MyriCOM Control Regs");
mp->lregs = of_ioremap(&op->resource[0], (256 * 1024),
PAGE_SIZE, "MyriCOM LANAI Regs");
mp->lanai = of_ioremap(&op->resource[0], (512 * 1024),
mp->eeprom.ramsz, "MyriCOM SRAM");
}
DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n",
mp->cregs, mp->lregs, mp->lanai));
if (mp->eeprom.cpuvers >= CPUVERS_4_0)
mp->shmem_base = 0xf000;
else
mp->shmem_base = 0x8000;
DET(("Shared memory base is %04x, ", mp->shmem_base));
mp->shmem = (struct myri_shmem __iomem *)
(mp->lanai + (mp->shmem_base * 2));
DET(("shmem mapped at %p\n", mp->shmem));
mp->rqack = &mp->shmem->channel.recvqa;
mp->rq = &mp->shmem->channel.recvq;
mp->sq = &mp->shmem->channel.sendq;
/* Reset the board. */
DET(("Resetting LANAI\n"));
myri_reset_off(mp->lregs, mp->cregs);
myri_reset_on(mp->cregs);
/* Turn IRQ's off. */
myri_disable_irq(mp->lregs, mp->cregs);
/* Reset once more. */
myri_reset_on(mp->cregs);
/* Get the supported DVMA burst sizes from our SBUS. */
mp->myri_bursts = of_getintprop_default(dp->parent,
"burst-sizes", 0x00);
if (!sbus_can_burst64())
mp->myri_bursts &= ~(DMA_BURST64);
DET(("MYRI bursts %02x\n", mp->myri_bursts));
/* Encode SBUS interrupt level in second control register. */
i = of_getintprop_default(dp, "interrupts", 0);
if (i == 0)
i = 4;
DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n",
i, (1 << i)));
sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL);
mp->dev = dev;
dev->watchdog_timeo = 5*HZ;
dev->irq = op->archdata.irqs[0];
dev->netdev_ops = &myri_ops;
/* Register interrupt handler now. */
DET(("Requesting MYRIcom IRQ line.\n"));
if (request_irq(dev->irq, myri_interrupt,
IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) {
;
goto err;
}
dev->mtu = MYRINET_MTU;
dev->header_ops = &myri_header_ops;
dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN);
/* Load code onto the LANai. */
DET(("Loading LANAI firmware\n"));
if (myri_load_lanai(mp)) {
;
goto err_free_irq;
}
if (register_netdev(dev)) {
;
goto err_free_irq;
}
dev_set_drvdata(&op->dev, mp);
num++;
// printk("%s: MyriCOM MyriNET Ethernet %pM\n",
;
return 0;
err_free_irq:
free_irq(dev->irq, dev);
err:
/* This will also free the co-allocated private data*/
free_netdev(dev);
return -ENODEV;
}
static int __devinit myri_load_lanai(struct myri_eth *mp)
{
const struct firmware *fw;
struct net_device *dev = mp->dev;
struct myri_shmem __iomem *shmem = mp->shmem;
void __iomem *rptr;
int i, lanai4_data_size;
myri_disable_irq(mp->lregs, mp->cregs);
myri_reset_on(mp->cregs);
rptr = mp->lanai;
for (i = 0; i < mp->eeprom.ramsz; i++)
sbus_writeb(0, rptr + i);
if (mp->eeprom.cpuvers >= CPUVERS_3_0)
sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL);
i = request_firmware(&fw, FWNAME, &mp->myri_op->dev);
if (i) {
// printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
;
return i;
}
if (fw->size < 2) {
// printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
;
release_firmware(fw);
return -EINVAL;
}
lanai4_data_size = fw->data[0] << 8 | fw->data[1];
/* Load executable code. */
for (i = 2; i < fw->size; i++)
sbus_writeb(fw->data[i], rptr++);
/* Load data segment. */
for (i = 0; i < lanai4_data_size; i++)
sbus_writeb(0, rptr++);
/* Set device address. */
sbus_writeb(0, &shmem->addr[0]);
sbus_writeb(0, &shmem->addr[1]);
for (i = 0; i < 6; i++)
sbus_writeb(dev->dev_addr[i],
&shmem->addr[i + 2]);
/* Set SBUS bursts and interrupt mask. */
sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst);
sbus_writel(SHMEM_IMASK_RX, &shmem->imask);
/* Release the LANAI. */
myri_disable_irq(mp->lregs, mp->cregs);
myri_reset_off(mp->lregs, mp->cregs);
myri_disable_irq(mp->lregs, mp->cregs);
/* Wait for the reset to complete. */
for (i = 0; i < 5000; i++) {
if (sbus_readl(&shmem->channel.state) != STATE_READY)
break;
else
udelay(10);
}
if (i == 5000)
;
i = myri_do_handshake(mp);
if (i)
;
if (mp->eeprom.cpuvers == CPUVERS_4_0)
sbus_writel(0, mp->lregs + LANAI_VERS);
release_firmware(fw);
return i;
}
static int __init myri_ether_init(struct net_device *dev, struct sbus_dev *sdev, int num)
{
static unsigned version_printed = 0;
struct myri_eth *mp;
unsigned char prop_buf[32];
int i;
DET(("myri_ether_init(%p,%p,%d):\n", dev, sdev, num));
dev = init_etherdev(0, sizeof(struct myri_eth));
if (version_printed++ == 0)
printk(version);
printk("%s: MyriCOM MyriNET Ethernet ", dev->name);
mp = (struct myri_eth *) dev->priv;
mp->myri_sdev = sdev;
/* Clean out skb arrays. */
for (i = 0; i < (RX_RING_SIZE + 1); i++)
mp->rx_skbs[i] = NULL;
for (i = 0; i < TX_RING_SIZE; i++)
mp->tx_skbs[i] = NULL;
/* First check for EEPROM information. */
i = prom_getproperty(sdev->prom_node, "myrinet-eeprom-info",
(char *)&mp->eeprom, sizeof(struct myri_eeprom));
DET(("prom_getprop(myrinet-eeprom-info) returns %d\n", i));
if (i == 0 || i == -1) {
/* No eeprom property, must cook up the values ourselves. */
DET(("No EEPROM: "));
mp->eeprom.bus_type = BUS_TYPE_SBUS;
mp->eeprom.cpuvers = prom_getintdefault(sdev->prom_node,"cpu_version",0);
mp->eeprom.cval = prom_getintdefault(sdev->prom_node,"clock_value",0);
mp->eeprom.ramsz = prom_getintdefault(sdev->prom_node,"sram_size",0);
DET(("cpuvers[%d] cval[%d] ramsz[%d]\n", mp->eeprom.cpuvers,
mp->eeprom.cval, mp->eeprom.ramsz));
if (mp->eeprom.cpuvers == 0) {
DET(("EEPROM: cpuvers was zero, setting to %04x\n",CPUVERS_2_3));
mp->eeprom.cpuvers = CPUVERS_2_3;
}
if (mp->eeprom.cpuvers < CPUVERS_3_0) {
DET(("EEPROM: cpuvers < CPUVERS_3_0, clockval set to zero.\n"));
mp->eeprom.cval = 0;
}
if (mp->eeprom.ramsz == 0) {
DET(("EEPROM: ramsz == 0, setting to 128k\n"));
mp->eeprom.ramsz = (128 * 1024);
}
i = prom_getproperty(sdev->prom_node, "myrinet-board-id",
&prop_buf[0], 10);
DET(("EEPROM: prom_getprop(myrinet-board-id) returns %d\n", i));
if ((i != 0) && (i != -1))
memcpy(&mp->eeprom.id[0], &prop_buf[0], 6);
else
set_boardid_from_idprom(mp, num);
i = prom_getproperty(sdev->prom_node, "fpga_version",
&mp->eeprom.fvers[0], 32);
DET(("EEPROM: prom_getprop(fpga_version) returns %d\n", i));
if (i == 0 || i == -1)
memset(&mp->eeprom.fvers[0], 0, 32);
if (mp->eeprom.cpuvers == CPUVERS_4_1) {
DET(("EEPROM: cpuvers CPUVERS_4_1, "));
if (mp->eeprom.ramsz == (128 * 1024)) {
DET(("ramsize 128k, setting to 256k, "));
mp->eeprom.ramsz = (256 * 1024);
}
if ((mp->eeprom.cval==0x40414041)||(mp->eeprom.cval==0x90449044)){
DET(("changing cval from %08x to %08x ",
mp->eeprom.cval, 0x50e450e4));
mp->eeprom.cval = 0x50e450e4;
}
DET(("\n"));
}
}
#ifdef DEBUG_DETECT
dump_eeprom(mp);
#endif
for (i = 0; i < 6; i++)
printk("%2.2x%c",
dev->dev_addr[i] = mp->eeprom.id[i],
i == 5 ? ' ' : ':');
printk("\n");
determine_reg_space_size(mp);
/* Map in the MyriCOM register/localram set. */
if (mp->eeprom.cpuvers < CPUVERS_4_0) {
/* XXX Makes no sense, if control reg is non-existant this
* XXX driver cannot function at all... maybe pre-4.0 is
* XXX only a valid version for PCI cards? Ask feldy...
*/
DET(("Mapping regs for cpuvers < CPUVERS_4_0\n"));
mp->regs = sbus_ioremap(&sdev->resource[0], 0,
mp->reg_size, "MyriCOM Regs");
if (!mp->regs) {
printk("MyriCOM: Cannot map MyriCOM registers.\n");
return -ENODEV;
}
mp->lanai = (unsigned short *) (mp->regs + (256 * 1024));
mp->lanai3 = (unsigned int *) mp->lanai;
mp->lregs = (unsigned long) &mp->lanai[0x10000];
} else {
DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n"));
mp->cregs = sbus_ioremap(&sdev->resource[0], 0,
PAGE_SIZE, "MyriCOM Control Regs");
mp->lregs = sbus_ioremap(&sdev->resource[0], (256 * 1024),
PAGE_SIZE, "MyriCOM LANAI Regs");
mp->lanai = (unsigned short *)
sbus_ioremap(&sdev->resource[0], (512 * 1024),
mp->eeprom.ramsz, "MyriCOM SRAM");
mp->lanai3 = (unsigned int *) mp->lanai;
}
DET(("Registers mapped: cregs[%lx] lregs[%lx] lanai[%p] lanai3[%p]\n",
mp->cregs, mp->lregs, mp->lanai, mp->lanai3));
if (mp->eeprom.cpuvers >= CPUVERS_4_0)
mp->shmem_base = 0xf000;
else
mp->shmem_base = 0x8000;
DET(("Shared memory base is %04x, ", mp->shmem_base));
mp->shmem = (struct myri_shmem *) &mp->lanai[mp->shmem_base];
DET(("shmem mapped at %p\n", mp->shmem));
mp->rqack = &mp->shmem->channel.recvqa;
mp->rq = &mp->shmem->channel.recvq;
mp->sq = &mp->shmem->channel.sendq;
/* Reset the board. */
DET(("Resetting LANAI\n"));
myri_reset_off(mp->lregs, mp->cregs);
myri_reset_on(mp->cregs);
/* Turn IRQ's off. */
myri_disable_irq(mp->lregs, mp->cregs);
/* Reset once more. */
myri_reset_on(mp->cregs);
/* Get the supported DVMA burst sizes from our SBUS. */
mp->myri_bursts = prom_getintdefault(mp->myri_sdev->bus->prom_node,
"burst-sizes", 0x00);
if (!sbus_can_burst64(sdev))
mp->myri_bursts &= ~(DMA_BURST64);
DET(("MYRI bursts %02x\n", mp->myri_bursts));
/* Encode SBUS interrupt level in second control register. */
i = prom_getint(sdev->prom_node, "interrupts");
if (i == 0)
i = 4;
DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n",
i, (1 << i)));
sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL);
mp->dev = dev;
dev->open = &myri_open;
dev->stop = &myri_close;
dev->hard_start_xmit = &myri_start_xmit;
dev->tx_timeout = &myri_tx_timeout;
dev->watchdog_timeo = 5*HZ;
dev->get_stats = &myri_get_stats;
dev->set_multicast_list = &myri_set_multicast;
dev->irq = sdev->irqs[0];
/* Register interrupt handler now. */
DET(("Requesting MYRIcom IRQ line.\n"));
if (request_irq(dev->irq, &myri_interrupt,
SA_SHIRQ, "MyriCOM Ethernet", (void *) dev)) {
printk("MyriCOM: Cannot register interrupt handler.\n");
return -ENODEV;
}
DET(("ether_setup()\n"));
ether_setup(dev);
dev->mtu = MYRINET_MTU;
dev->change_mtu = myri_change_mtu;
dev->hard_header = myri_header;
dev->rebuild_header = myri_rebuild_header;
dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN);
dev->hard_header_cache = myri_header_cache;
dev->header_cache_update= myri_header_cache_update;
/* Load code onto the LANai. */
DET(("Loading LANAI firmware\n"));
myri_load_lanai(mp);
#ifdef MODULE
dev->ifindex = dev_new_index();
mp->next_module = root_myri_dev;
root_myri_dev = mp;
#endif
return 0;
}
static int myri_load_lanai(struct myri_eth *mp)
{
struct net_device *dev = mp->dev;
struct myri_shmem *shmem = mp->shmem;
unsigned char *rptr;
int i;
myri_disable_irq(mp->lregs, mp->cregs);
myri_reset_on(mp->cregs);
rptr = (unsigned char *) mp->lanai;
for (i = 0; i < mp->eeprom.ramsz; i++)
sbus_writeb(0, &rptr[i]);
if (mp->eeprom.cpuvers >= CPUVERS_3_0)
sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL);
/* Load executable code. */
for (i = 0; i < sizeof(lanai4_code); i++)
sbus_writeb(lanai4_code[i], &rptr[(lanai4_code_off * 2) + i]);
/* Load data segment. */
for (i = 0; i < sizeof(lanai4_data); i++)
sbus_writeb(lanai4_data[i], &rptr[(lanai4_data_off * 2) + i]);
/* Set device address. */
sbus_writeb(0, &shmem->addr[0]);
sbus_writeb(0, &shmem->addr[1]);
for (i = 0; i < 6; i++)
sbus_writeb(dev->dev_addr[i],
&shmem->addr[i + 2]);
/* Set SBUS bursts and interrupt mask. */
sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst);
sbus_writel(SHMEM_IMASK_RX, &shmem->imask);
/* Release the LANAI. */
myri_disable_irq(mp->lregs, mp->cregs);
myri_reset_off(mp->lregs, mp->cregs);
myri_disable_irq(mp->lregs, mp->cregs);
/* Wait for the reset to complete. */
for (i = 0; i < 5000; i++) {
if (sbus_readl(&shmem->channel.state) != STATE_READY)
break;
else
udelay(10);
}
if (i == 5000)
printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n");
i = myri_do_handshake(mp);
if (i)
printk(KERN_ERR "myricom: Handshake with LANAI failed.\n");
if (mp->eeprom.cpuvers == CPUVERS_4_0)
sbus_writel(0, mp->lregs + LANAI_VERS);
return i;
}
static int __devinit myri_sbus_probe(struct of_device *op, const struct of_device_id *match)
{
struct device_node *dp = op->node;
static unsigned version_printed;
struct net_device *dev;
struct myri_eth *mp;
const void *prop;
static int num;
int i, len;
DET(("myri_ether_init(%p,%d):\n", op, num));
dev = alloc_etherdev(sizeof(struct myri_eth));
if (!dev)
return -ENOMEM;
if (version_printed++ == 0)
printk(version);
SET_NETDEV_DEV(dev, &op->dev);
mp = netdev_priv(dev);
spin_lock_init(&mp->irq_lock);
mp->myri_op = op;
for (i = 0; i < (RX_RING_SIZE + 1); i++)
mp->rx_skbs[i] = NULL;
for (i = 0; i < TX_RING_SIZE; i++)
mp->tx_skbs[i] = NULL;
prop = of_get_property(dp, "myrinet-eeprom-info", &len);
if (prop)
memcpy(&mp->eeprom, prop, sizeof(struct myri_eeprom));
if (!prop) {
DET(("No EEPROM: "));
mp->eeprom.bus_type = BUS_TYPE_SBUS;
mp->eeprom.cpuvers =
of_getintprop_default(dp, "cpu_version", 0);
mp->eeprom.cval =
of_getintprop_default(dp, "clock_value", 0);
mp->eeprom.ramsz = of_getintprop_default(dp, "sram_size", 0);
if (!mp->eeprom.cpuvers)
mp->eeprom.cpuvers = CPUVERS_2_3;
if (mp->eeprom.cpuvers < CPUVERS_3_0)
mp->eeprom.cval = 0;
if (!mp->eeprom.ramsz)
mp->eeprom.ramsz = (128 * 1024);
prop = of_get_property(dp, "myrinet-board-id", &len);
if (prop)
memcpy(&mp->eeprom.id[0], prop, 6);
else
set_boardid_from_idprom(mp, num);
prop = of_get_property(dp, "fpga_version", &len);
if (prop)
memcpy(&mp->eeprom.fvers[0], prop, 32);
else
memset(&mp->eeprom.fvers[0], 0, 32);
if (mp->eeprom.cpuvers == CPUVERS_4_1) {
if (mp->eeprom.ramsz == (128 * 1024))
mp->eeprom.ramsz = (256 * 1024);
if ((mp->eeprom.cval == 0x40414041) ||
(mp->eeprom.cval == 0x90449044))
mp->eeprom.cval = 0x50e450e4;
}
}
#ifdef DEBUG_DETECT
dump_eeprom(mp);
#endif
for (i = 0; i < 6; i++)
dev->dev_addr[i] = mp->eeprom.id[i];
determine_reg_space_size(mp);
if (mp->eeprom.cpuvers < CPUVERS_4_0) {
DET(("Mapping regs for cpuvers < CPUVERS_4_0\n"));
mp->regs = of_ioremap(&op->resource[0], 0,
mp->reg_size, "MyriCOM Regs");
if (!mp->regs) {
printk("MyriCOM: Cannot map MyriCOM registers.\n");
goto err;
}
mp->lanai = mp->regs + (256 * 1024);
mp->lregs = mp->lanai + (0x10000 * 2);
} else {
DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n"));
mp->cregs = of_ioremap(&op->resource[0], 0,
PAGE_SIZE, "MyriCOM Control Regs");
mp->lregs = of_ioremap(&op->resource[0], (256 * 1024),
PAGE_SIZE, "MyriCOM LANAI Regs");
mp->lanai = of_ioremap(&op->resource[0], (512 * 1024),
mp->eeprom.ramsz, "MyriCOM SRAM");
}
DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n",
mp->cregs, mp->lregs, mp->lanai));
if (mp->eeprom.cpuvers >= CPUVERS_4_0)
mp->shmem_base = 0xf000;
else
mp->shmem_base = 0x8000;
DET(("Shared memory base is %04x, ", mp->shmem_base));
mp->shmem = (struct myri_shmem __iomem *)
(mp->lanai + (mp->shmem_base * 2));
DET(("shmem mapped at %p\n", mp->shmem));
mp->rqack = &mp->shmem->channel.recvqa;
mp->rq = &mp->shmem->channel.recvq;
mp->sq = &mp->shmem->channel.sendq;
DET(("Resetting LANAI\n"));
myri_reset_off(mp->lregs, mp->cregs);
myri_reset_on(mp->cregs);
myri_disable_irq(mp->lregs, mp->cregs);
myri_reset_on(mp->cregs);
mp->myri_bursts = of_getintprop_default(dp->parent,
"burst-sizes", 0x00);
if (!sbus_can_burst64())
mp->myri_bursts &= ~(DMA_BURST64);
DET(("MYRI bursts %02x\n", mp->myri_bursts));
i = of_getintprop_default(dp, "interrupts", 0);
if (i == 0)
i = 4;
DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n",
i, (1 << i)));
sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL);
mp->dev = dev;
dev->watchdog_timeo = 5*HZ;
dev->irq = op->irqs[0];
dev->netdev_ops = &myri_ops;
DET(("Requesting MYRIcom IRQ line.\n"));
if (request_irq(dev->irq, &myri_interrupt,
IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) {
printk("MyriCOM: Cannot register interrupt handler.\n");
goto err;
}
dev->mtu = MYRINET_MTU;
dev->header_ops = &myri_header_ops;
dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN);
DET(("Loading LANAI firmware\n"));
if (myri_load_lanai(mp)) {
printk(KERN_ERR "MyriCOM: Cannot Load LANAI firmware.\n");
goto err_free_irq;
}
if (register_netdev(dev)) {
printk("MyriCOM: Cannot register device.\n");
goto err_free_irq;
}
dev_set_drvdata(&op->dev, mp);
num++;
printk("%s: MyriCOM MyriNET Ethernet %pM\n",
dev->name, dev->dev_addr);
return 0;
err_free_irq:
free_irq(dev->irq, dev);
err:
free_netdev(dev);
return -ENODEV;
}
static int __devinit myri_load_lanai(struct myri_eth *mp)
{
const struct firmware *fw;
struct net_device *dev = mp->dev;
struct myri_shmem __iomem *shmem = mp->shmem;
void __iomem *rptr;
int i, lanai4_data_size;
myri_disable_irq(mp->lregs, mp->cregs);
myri_reset_on(mp->cregs);
rptr = mp->lanai;
for (i = 0; i < mp->eeprom.ramsz; i++)
sbus_writeb(0, rptr + i);
if (mp->eeprom.cpuvers >= CPUVERS_3_0)
sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL);
i = request_firmware(&fw, FWNAME, &mp->myri_op->dev);
if (i) {
printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
FWNAME, i);
return i;
}
if (fw->size < 2) {
printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
fw->size, FWNAME);
release_firmware(fw);
return -EINVAL;
}
lanai4_data_size = fw->data[0] << 8 | fw->data[1];
for (i = 2; i < fw->size; i++)
sbus_writeb(fw->data[i], rptr++);
for (i = 0; i < lanai4_data_size; i++)
sbus_writeb(0, rptr++);
sbus_writeb(0, &shmem->addr[0]);
sbus_writeb(0, &shmem->addr[1]);
for (i = 0; i < 6; i++)
sbus_writeb(dev->dev_addr[i],
&shmem->addr[i + 2]);
sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst);
sbus_writel(SHMEM_IMASK_RX, &shmem->imask);
myri_disable_irq(mp->lregs, mp->cregs);
myri_reset_off(mp->lregs, mp->cregs);
myri_disable_irq(mp->lregs, mp->cregs);
for (i = 0; i < 5000; i++) {
if (sbus_readl(&shmem->channel.state) != STATE_READY)
break;
else
udelay(10);
}
if (i == 5000)
printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n");
i = myri_do_handshake(mp);
if (i)
printk(KERN_ERR "myricom: Handshake with LANAI failed.\n");
if (mp->eeprom.cpuvers == CPUVERS_4_0)
sbus_writel(0, mp->lregs + LANAI_VERS);
release_firmware(fw);
return i;
}
