static int macronix_nand_init(struct nand_chip *chip) { if (nand_is_slc(chip)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; /* * MX30LF2G18AC chip does not support using SET/GET_FEATURES to change * the timings unlike what is declared in the parameter page. Unflag * this feature to avoid unnecessary downturns. */ if (chip->parameters.supports_set_get_features && !strcmp("MX30LF2G18AC", chip->parameters.model)) { bitmap_clear(chip->parameters.get_feature_list, ONFI_FEATURE_ADDR_TIMING_MODE, 1); bitmap_clear(chip->parameters.set_feature_list, ONFI_FEATURE_ADDR_TIMING_MODE, 1); } return 0; }
int denali_init(struct denali_nand_info *denali) { int ret; if (denali->platform == INTEL_CE4100) { /* Due to a silicon limitation, we can only support * ONFI timing mode 1 and below. */ if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); return -EINVAL; } } /* Is 32-bit DMA supported? */ ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); if (ret) { pr_err("Spectra: no usable DMA configuration\n"); return ret; } denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, DENALI_BUF_SIZE, DMA_BIDIRECTIONAL); if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { dev_err(denali->dev, "Spectra: failed to map DMA buffer\n"); return -EIO; } denali->mtd.dev.parent = denali->dev; denali_hw_init(denali); denali_drv_init(denali); /* denali_isr register is done after all the hardware * initilization is finished*/ if (request_irq(denali->irq, denali_isr, IRQF_SHARED, DENALI_NAND_NAME, denali)) { pr_err("Spectra: Unable to allocate IRQ\n"); return -ENODEV; } /* now that our ISR is registered, we can enable interrupts */ denali_set_intr_modes(denali, true); denali->mtd.name = "denali-nand"; denali->mtd.owner = THIS_MODULE; denali->mtd.priv = &denali->nand; /* register the driver with the NAND core subsystem */ denali->nand.select_chip = denali_select_chip; denali->nand.cmdfunc = denali_cmdfunc; denali->nand.read_byte = denali_read_byte; denali->nand.waitfunc = denali_waitfunc; /* scan for NAND devices attached to the controller * this is the first stage in a two step process to register * with the nand subsystem */ if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { ret = -ENXIO; goto failed_req_irq; } /* MTD supported page sizes vary by kernel. We validate our * kernel supports the device here. */ if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) { ret = -ENODEV; pr_err("Spectra: device size not supported by this version of MTD."); goto failed_req_irq; } /* support for multi nand * MTD known nothing about multi nand, * so we should tell it the real pagesize * and anything necessery */ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); denali->nand.chipsize <<= (denali->devnum - 1); denali->nand.page_shift += (denali->devnum - 1); denali->nand.pagemask = (denali->nand.chipsize >> denali->nand.page_shift) - 1; denali->nand.bbt_erase_shift += (denali->devnum - 1); denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; denali->nand.chip_shift += (denali->devnum - 1); denali->mtd.writesize <<= (denali->devnum - 1); denali->mtd.oobsize <<= (denali->devnum - 1); denali->mtd.erasesize <<= (denali->devnum - 1); denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; denali->bbtskipbytes *= denali->devnum; /* second stage of the NAND scan * this stage requires information regarding ECC and * bad block management. */ /* Bad block management */ denali->nand.bbt_td = &bbt_main_descr; denali->nand.bbt_md = &bbt_mirror_descr; /* skip the scan for now until we have OOB read and write support */ denali->nand.bbt_options |= NAND_BBT_USE_FLASH; denali->nand.options |= NAND_SKIP_BBTSCAN; denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; /* Denali Controller only support 15bit and 8bit ECC in MRST, * so just let controller do 15bit ECC for MLC and 8bit ECC for * SLC if possible. * */ if (!nand_is_slc(&denali->nand) && (denali->mtd.oobsize > (denali->bbtskipbytes + ECC_15BITS * (denali->mtd.writesize / ECC_SECTOR_SIZE)))) { /* if MLC OOB size is large enough, use 15bit ECC*/ denali->nand.ecc.strength = 15; denali->nand.ecc.layout = &nand_15bit_oob; denali->nand.ecc.bytes = ECC_15BITS; iowrite32(15, denali->flash_reg + ECC_CORRECTION); } else if (denali->mtd.oobsize < (denali->bbtskipbytes + ECC_8BITS * (denali->mtd.writesize / ECC_SECTOR_SIZE))) { pr_err("Your NAND chip OOB is not large enough to \ contain 8bit ECC correction codes"); goto failed_req_irq; } else {
int denali_init(struct denali_nand_info *denali) { struct mtd_info *mtd = nand_to_mtd(&denali->nand); int ret; if (denali->platform == INTEL_CE4100) { /* * Due to a silicon limitation, we can only support * ONFI timing mode 1 and below. */ if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); return -EINVAL; } } /* allocate a temporary buffer for nand_scan_ident() */ denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE, GFP_DMA | GFP_KERNEL); if (!denali->buf.buf) return -ENOMEM; mtd->dev.parent = denali->dev; denali_hw_init(denali); denali_drv_init(denali); /* Request IRQ after all the hardware initialization is finished */ ret = devm_request_irq(denali->dev, denali->irq, denali_isr, IRQF_SHARED, DENALI_NAND_NAME, denali); if (ret) { dev_err(denali->dev, "Unable to request IRQ\n"); return ret; } /* now that our ISR is registered, we can enable interrupts */ denali_set_intr_modes(denali, true); mtd->name = "denali-nand"; /* register the driver with the NAND core subsystem */ denali->nand.select_chip = denali_select_chip; denali->nand.cmdfunc = denali_cmdfunc; denali->nand.read_byte = denali_read_byte; denali->nand.waitfunc = denali_waitfunc; /* * scan for NAND devices attached to the controller * this is the first stage in a two step process to register * with the nand subsystem */ ret = nand_scan_ident(mtd, denali->max_banks, NULL); if (ret) goto failed_req_irq; /* allocate the right size buffer now */ devm_kfree(denali->dev, denali->buf.buf); denali->buf.buf = devm_kzalloc(denali->dev, mtd->writesize + mtd->oobsize, GFP_KERNEL); if (!denali->buf.buf) { ret = -ENOMEM; goto failed_req_irq; } /* Is 32-bit DMA supported? */ ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32)); if (ret) { dev_err(denali->dev, "No usable DMA configuration\n"); goto failed_req_irq; } denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf, mtd->writesize + mtd->oobsize, DMA_BIDIRECTIONAL); if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) { dev_err(denali->dev, "Failed to map DMA buffer\n"); ret = -EIO; goto failed_req_irq; } /* * support for multi nand * MTD known nothing about multi nand, so we should tell it * the real pagesize and anything necessery */ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); denali->nand.chipsize <<= denali->devnum - 1; denali->nand.page_shift += denali->devnum - 1; denali->nand.pagemask = (denali->nand.chipsize >> denali->nand.page_shift) - 1; denali->nand.bbt_erase_shift += denali->devnum - 1; denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; denali->nand.chip_shift += denali->devnum - 1; mtd->writesize <<= denali->devnum - 1; mtd->oobsize <<= denali->devnum - 1; mtd->erasesize <<= denali->devnum - 1; mtd->size = denali->nand.numchips * denali->nand.chipsize; denali->bbtskipbytes *= denali->devnum; /* * second stage of the NAND scan * this stage requires information regarding ECC and * bad block management. */ /* Bad block management */ denali->nand.bbt_td = &bbt_main_descr; denali->nand.bbt_md = &bbt_mirror_descr; /* skip the scan for now until we have OOB read and write support */ denali->nand.bbt_options |= NAND_BBT_USE_FLASH; denali->nand.options |= NAND_SKIP_BBTSCAN; denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; /* no subpage writes on denali */ denali->nand.options |= NAND_NO_SUBPAGE_WRITE; /* * Denali Controller only support 15bit and 8bit ECC in MRST, * so just let controller do 15bit ECC for MLC and 8bit ECC for * SLC if possible. * */ if (!nand_is_slc(&denali->nand) && (mtd->oobsize > (denali->bbtskipbytes + ECC_15BITS * (mtd->writesize / ECC_SECTOR_SIZE)))) { /* if MLC OOB size is large enough, use 15bit ECC*/ denali->nand.ecc.strength = 15; denali->nand.ecc.bytes = ECC_15BITS; iowrite32(15, denali->flash_reg + ECC_CORRECTION); } else if (mtd->oobsize < (denali->bbtskipbytes + ECC_8BITS * (mtd->writesize / ECC_SECTOR_SIZE))) { pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); goto failed_req_irq; } else { denali->nand.ecc.strength = 8; denali->nand.ecc.bytes = ECC_8BITS; iowrite32(8, denali->flash_reg + ECC_CORRECTION); } mtd_set_ooblayout(mtd, &denali_ooblayout_ops); denali->nand.ecc.bytes *= denali->devnum; denali->nand.ecc.strength *= denali->devnum; /* override the default read operations */ denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; denali->nand.ecc.read_page = denali_read_page; denali->nand.ecc.read_page_raw = denali_read_page_raw; denali->nand.ecc.write_page = denali_write_page; denali->nand.ecc.write_page_raw = denali_write_page_raw; denali->nand.ecc.read_oob = denali_read_oob; denali->nand.ecc.write_oob = denali_write_oob; denali->nand.erase = denali_erase; ret = nand_scan_tail(mtd); if (ret) goto failed_req_irq; ret = mtd_device_register(mtd, NULL, 0); if (ret) { dev_err(denali->dev, "Failed to register MTD: %d\n", ret); goto failed_req_irq; } return 0; failed_req_irq: denali_irq_cleanup(denali->irq, denali); return ret; }
int denali_init(struct denali_nand_info *denali) { int ret = 0; uint32_t val; if (denali->platform == INTEL_CE4100) { /* * Due to a silicon limitation, we can only support * ONFI timing mode 1 and below. */ if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); return -EINVAL; } } /* allocate a temporary buffer for nand_scan_ident() */ denali->buf.buf = kzalloc(PAGE_SIZE, GFP_DMA | GFP_KERNEL); if (!denali->buf.buf) return -ENOMEM; denali->mtd.parent = denali->dev; denali_hw_init(denali); denali_drv_init(denali); denali_set_intr_modes(denali, true); denali->mtd.name = "denali-nand"; denali->mtd.priv = &denali->nand; /* register the driver with the NAND core subsystem */ denali->nand.read_buf = denali_read_buf; denali->nand.select_chip = denali_select_chip; denali->nand.cmdfunc = denali_cmdfunc; denali->nand.read_byte = denali_read_byte; denali->nand.waitfunc = denali_waitfunc; /* * scan for NAND devices attached to the controller * this is the first stage in a two step process to register * with the nand subsystem */ if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { ret = -ENXIO; goto failed_req_irq; } /* allocate the right size buffer now */ kfree(denali->buf.buf); denali->buf.buf = kzalloc(denali->mtd.writesize + denali->mtd.oobsize, GFP_KERNEL); if (!denali->buf.buf) { ret = -ENOMEM; goto failed_req_irq; } /* * support for multi nand * MTD known nothing about multi nand, so we should tell it * the real pagesize and anything necessery */ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); denali->nand.chipsize <<= (denali->devnum - 1); denali->nand.page_shift += (denali->devnum - 1); denali->nand.pagemask = (denali->nand.chipsize >> denali->nand.page_shift) - 1; denali->nand.bbt_erase_shift += (denali->devnum - 1); denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; denali->nand.chip_shift += (denali->devnum - 1); denali->mtd.writesize <<= (denali->devnum - 1); denali->mtd.oobsize <<= (denali->devnum - 1); denali->mtd.erasesize <<= (denali->devnum - 1); denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; denali->bbtskipbytes *= denali->devnum; /* * second stage of the NAND scan * this stage requires information regarding ECC and * bad block management. */ /* Bad block table description is set by nand framework, see nand_bbt.c */ denali->nand.bbt_options |= NAND_BBT_USE_FLASH; denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; if (denali->have_hw_ecc_fixup) { /* We have OOB support, so allow scan of BBT and leave the OOB alone */ denali->nand.bbt_options |= NAND_BBT_NO_OOB; } else { /* skip the scan for now until we have OOB read and write support */ denali->nand.options |= NAND_SKIP_BBTSCAN; } /* no subpage writes on denali */ denali->nand.options |= NAND_NO_SUBPAGE_WRITE; /* * Denali Controller only support 15bit and 8bit ECC in MRST, * so just let controller do 15bit ECC for MLC and 8bit ECC for * SLC if possible. * */ if (!nand_is_slc(&denali->nand) && (denali->mtd.oobsize > (denali->bbtskipbytes + ECC_15BITS * (denali->mtd.writesize / ECC_SECTOR_SIZE)))) { /* if MLC OOB size is large enough, use 15bit ECC*/ denali->nand.ecc.strength = 15; denali->nand.ecc.layout = &nand_15bit_oob; denali->nand.ecc.bytes = ECC_15BITS; iowrite32(15, denali->flash_reg + ECC_CORRECTION); } else if (denali->mtd.oobsize < (denali->bbtskipbytes + ECC_8BITS * (denali->mtd.writesize / ECC_SECTOR_SIZE))) { pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); goto failed_req_irq; } else { denali->nand.ecc.strength = 8; denali->nand.ecc.layout = &nand_8bit_oob; denali->nand.ecc.bytes = ECC_8BITS; iowrite32(8, denali->flash_reg + ECC_CORRECTION); } denali->nand.ecc.bytes *= denali->devnum; denali->nand.ecc.strength *= denali->devnum; denali->nand.ecc.layout->eccbytes *= denali->mtd.writesize / ECC_SECTOR_SIZE; denali->nand.ecc.layout->oobfree[0].offset = denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; denali->nand.ecc.layout->oobfree[0].length = denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - denali->bbtskipbytes; /* * Let driver know the total blocks number and how many blocks * contained by each nand chip. blksperchip will help driver to * know how many blocks is taken by FW. */ denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift; denali->blksperchip = denali->totalblks / denali->nand.numchips; /* override the default read operations */ denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; denali->nand.ecc.read_page = denali_read_page; denali->nand.ecc.read_page_raw = denali_read_page_raw; denali->nand.ecc.write_page = denali_write_page; denali->nand.ecc.write_page_raw = denali_write_page_raw; denali->nand.ecc.read_oob = denali_read_oob; denali->nand.ecc.write_oob = denali_write_oob; /* Occasionally the controller is in SPARE or MAIN+SPARE mode upon startup, and we want it to be MAIN only */ val = ioread32(denali->flash_reg + TRANSFER_MODE); if (val != 0) { int i; dev_dbg(denali->dev, "setting TRANSFER_MODE (%08x) back to MAIN only\n", val); /* put all banks in MAIN mode, no SPARE */ iowrite32(0, denali->flash_reg + TRANSFER_SPARE_REG); for (i = 0; i < 4; i++) index_addr(denali, MODE_10 | BANK(i) | 1, MAIN_ACCESS); } if (nand_scan_tail(&denali->mtd)) { ret = -ENXIO; goto failed_req_irq; } return add_mtd_nand_device(&denali->mtd, "nand"); failed_req_irq: denali_irq_cleanup(denali->irq, denali); return ret; }