int nand_erase(int bank, int block) {
int pageAddr;
if(bank >= Data.banksTotal)
return ERROR_ARG;
if(block >= Data.blocksPerBank)
return ERROR_ARG;
pageAddr = block * Data.pagesPerBlock;
SET_REG(NAND + NAND_CONFIG,
((NANDSetting1 & NAND_CONFIG_SETTING1MASK) << NAND_CONFIG_SETTING1SHIFT) | ((NANDSetting2 & NAND_CONFIG_SETTING2MASK) << NAND_CONFIG_SETTING2SHIFT)
| (1 << (banksTable[bank] + 1)) | NAND_CONFIG_DEFAULTS);
SET_REG(NAND + NAND_CON, 0x7E0);
SET_REG(NAND + NAND_CMD, 0x60);
SET_REG(NAND + NAND_CONFIG4, 2);
SET_REG(NAND + NAND_CONFIG3, pageAddr);
SET_REG(NAND + NAND_CON, NAND_CON_ADDRESSDONE);
if(wait_for_address_complete(500) != 0) {
bufferPrintf("nand (nand_erase): wait for address complete failed\r\n");
goto FIL_erase_error;
}
SET_REG(NAND + NAND_CMD, 0xD0);
wait_for_ready(500);
while((nand_read_status() & (1 << 6)) == 0);
if(nand_read_status() & 0x1)
return -1;
else
return 0;
FIL_erase_error:
return -1;
}
int nand_erase(int bank, int block) {
int pageAddr;
if(bank >= Geometry.banksTotal)
return ERROR_ARG;
if(block >= Geometry.blocksPerBank)
return ERROR_ARG;
pageAddr = block * Geometry.pagesPerBlock;
SET_REG(NAND + FMCTRL0,
((WEHighHoldTime & FMCTRL_TWH_MASK) << FMCTRL_TWH_SHIFT) | ((WPPulseTime & FMCTRL_TWP_MASK) << FMCTRL_TWP_SHIFT)
| (1 << (banksTable[bank] + 1)) | FMCTRL0_ON | FMCTRL0_WPB);
SET_REG(NAND + FMCTRL1, FMCTRL1_CLEARALL);
SET_REG(NAND + NAND_CMD, 0x60);
SET_REG(NAND + FMANUM, 2);
SET_REG(NAND + FMADDR0, pageAddr);
SET_REG(NAND + FMCTRL1, FMCTRL1_DOTRANSADDR);
if(wait_for_address_done(500) != 0) {
bufferPrintf("nand (nand_erase): wait for address complete failed\r\n");
goto FIL_erase_error;
}
SET_REG(NAND + NAND_CMD, 0xD0);
wait_for_ready(500);
while((nand_read_status() & (1 << 6)) == 0);
if(nand_read_status() & 0x1)
return -1;
else
return 0;
FIL_erase_error:
return -1;
}
void cmd_nand_status(int agc, char** argv) {
bufferPrintf("nand status: %x\r\n", nand_read_status());
}
