/*
* rs690_nb_post_init :
* rs690 NorthBridge init after PCI emulation
*/
void nb_post_init(void)
{
pcitag_t igfx_dev = _pci_make_tag(1, 5, 0);
DEBUG_INFO("\n++++++++++++++++++++NB POST STAGE WITH REV(%d)+++++++++++++++++++++++++++++++++\n", get_nb_revision());
#if defined(CFG_UMA_SUPPORT) || defined(CFG_SP_ENABLE)
/* gfx_late_init */
if( (ati_nb_cfg.gfx_config & (GFX_UMA_ENABLE | GFX_SP_ENABLE)) && (ati_nb_cfg.ext_config & EXT_GFX_SVIEW_ENABLE) ){
set_nbcfg_enable_bits(igfx_dev, 0x04, 1 << 1, 1 << 1); // enabel memory access
}
#endif
/* NB misc clock setting, powerdown as needed */
nb_misc_clock();
/* lock the whole NB registers */
nb_lock();
DEBUG_INFO("---------------------------------------------- NB POST STAGE DONE------------------------------\n");
return;
}
void smbrdr_lock_transport() { nb_lock(); }