static void acpi_create_gnvs(global_nvs_t *gnvs) { gnvs->pcnt = dev_count_cpu(); /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; /* Disable USB ports in S5 */ gnvs->s5u0 = 0; gnvs->s5u1 = 0; /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); /* TPM Present */ gnvs->tpmp = 1; /* Enable DPTF */ gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tact = ACTIVE_TEMPERATURE; gnvs->dpte = 1; #if CONFIG_CHROMEOS chromeos_init_vboot(&(gnvs->chromeos)); gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); }
static void acpi_create_gnvs(global_nvs_t *gnvs) { gnvs->pcnt = dev_count_cpu(); /* Enable USB ports in S3 */ gnvs->s3u0 = 1; gnvs->s3u1 = 1; /* Disable USB ports in S5 */ gnvs->s5u0 = 0; gnvs->s5u1 = 0; /* CBMEM TOC */ gnvs->cmem = 0; /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); /* TPM Present */ gnvs->tpmp = 1; #if CONFIG_CHROMEOS chromeos_init_vboot(&(gnvs->chromeos)); /* Bayley Bay does not have a Chrome EC */ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; #endif /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); }
static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; unsigned long bmbound_hi; unsigned long smmrrh; unsigned long smmrrl; unsigned long base_k, size_k; const unsigned long four_gig_kib = (4 << (30 - 10)); int index = 0; /* Read standard PCI resources. */ pci_dev_read_resources(dev); /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); /* 0 -> 0xa0000 */ base_k = RES_IN_KiB(0); size_k = RES_IN_KiB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); /* The SMMRR registers are 1MiB granularity with smmrrh being * inclusive of the SMM region. */ smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; /* 0xc0000 -> smrrl - cacheable and usable */ base_k = RES_IN_KiB(0xc0000); size_k = smmrrl - base_k; ram_resource(dev, index++, base_k, size_k); if (smmrrh > smmrrl) reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); /* All address space between bmbound and smmrrh is unusable. */ bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); /* The BMBOUND_HI register matches register bits of 31:24 with address * bits of 35:28. Therefore, shift register to align properly. */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); }
void acpi_init_gnvs(global_nvs_t *gnvs) { /* CPU core count */ gnvs->pcnt = dev_count_cpu(); /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); #if IS_ENABLED(CONFIG_CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif }