static inline void neo_set_cts_flow_control(struct channel_t *ch)
{
unsigned char ier = readb(&ch->ch_neo_uart->ier);
unsigned char efr = readb(&ch->ch_neo_uart->efr);
/* Turn on auto CTS flow control */
#if 1
ier |= UART_17158_IER_CTSDSR;
#else
ier &= ~(UART_17158_IER_CTSDSR);
#endif
efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
/* Turn off auto Xon flow control */
efr &= ~UART_17158_EFR_IXON;
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
/* Turn on table D, with 8 char hi/low watermarks */
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
/* Feed the UART our trigger levels */
writeb(8, &ch->ch_neo_uart->tfifo);
ch->ch_t_tlevel = 8;
writeb(ier, &ch->ch_neo_uart->ier);
neo_pci_posting_flush(ch->ch_bd);
}
static inline void neo_set_ixon_flow_control(struct channel_t *ch)
{
unsigned char ier = readb(&ch->ch_neo_uart->ier);
unsigned char efr = readb(&ch->ch_neo_uart->efr);
/* Turn off auto CTS flow control */
ier &= ~UART_17158_IER_CTSDSR;
efr &= ~UART_17158_EFR_CTSDSR;
/* Turn on auto Xon flow control */
efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
ch->ch_r_watermark = 4;
writeb(32, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 32;
/* Tell UART what start/stop chars it should be looking for */
writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
writeb(0, &ch->ch_neo_uart->xonchar2);
writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
writeb(0, &ch->ch_neo_uart->xoffchar2);
writeb(ier, &ch->ch_neo_uart->ier);
neo_pci_posting_flush(ch->ch_bd);
}
/*
* No locks are assumed to be held when calling this function.
*/
static inline void neo_clear_break(struct channel_t *ch, int force)
{
unsigned long flags;
spin_lock_irqsave(&ch->ch_lock, flags);
/* Bail if we aren't currently sending a break. */
if (!ch->ch_stop_sending_break) {
spin_unlock_irqrestore(&ch->ch_lock, flags);
return;
}
/* Turn break off, and unset some variables */
if (ch->ch_flags & CH_BREAK_SENDING) {
if (time_after_eq(jiffies, ch->ch_stop_sending_break)
|| force) {
unsigned char temp = readb(&ch->ch_neo_uart->lcr);
writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
neo_pci_posting_flush(ch->ch_bd);
ch->ch_flags &= ~(CH_BREAK_SENDING);
ch->ch_stop_sending_break = 0;
}
}
spin_unlock_irqrestore(&ch->ch_lock, flags);
}
/* Make the UART raise any of the output signals we want up */
static void neo_assert_modem_signals(struct jsm_channel *ch)
{
if (!ch)
return;
writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
/* change UARTs start/stop chars */
static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
{
/* if hardware flow control is set, then skip this whole thing */
if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
return;
/* Tell UART what start/stop chars it should be looking for */
writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
writeb(0, &ch->ch_neo_uart->xonchar2);
writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
writeb(0, &ch->ch_neo_uart->xoffchar2);
neo_pci_posting_flush(ch->ch_bd);
}
/*
* No locks are assumed to be held when calling this function.
*/
static void neo_clear_break(struct jsm_channel *ch, int force)
{
unsigned long lock_flags;
spin_lock_irqsave(&ch->ch_lock, lock_flags);
/* Turn break off, and unset some variables */
if (ch->ch_flags & CH_BREAK_SENDING) {
u8 temp = readb(&ch->ch_neo_uart->lcr);
writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
ch->ch_flags &= ~(CH_BREAK_SENDING);
jsm_printk(IOCTL, INFO, &ch->ch_bd->pci_dev,
"clear break Finishing UART_LCR_SBC! finished: %lx\n", jiffies);
/* flush write operation */
neo_pci_posting_flush(ch->ch_bd);
}
spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
}
static inline void neo_set_rts_flow_control(struct channel_t *ch)
{
unsigned char ier = readb(&ch->ch_neo_uart->ier);
unsigned char efr = readb(&ch->ch_neo_uart->efr);
/* Turn on auto RTS flow control */
#if 1
ier |= UART_17158_IER_RTSDTR;
#else
ier &= ~(UART_17158_IER_RTSDTR);
#endif
efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
/* Turn off auto Xoff flow control */
ier &= ~UART_17158_IER_XOFF;
efr &= ~UART_17158_EFR_IXOFF;
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
ch->ch_r_watermark = 4;
writeb(32, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 32;
writeb(ier, &ch->ch_neo_uart->ier);
/*
* From the Neo UART spec sheet:
* The auto RTS/DTR function must be started by asserting
* RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
* it is enabled.
*/
ch->ch_mostat |= UART_MCR_RTS;
neo_pci_posting_flush(ch->ch_bd);
}
static inline void neo_set_no_input_flow_control(struct channel_t *ch)
{
unsigned char ier = readb(&ch->ch_neo_uart->ier);
unsigned char efr = readb(&ch->ch_neo_uart->efr);
/* Turn off auto RTS flow control */
ier &= ~UART_17158_IER_RTSDTR;
efr &= ~UART_17158_EFR_RTSDTR;
/* Turn off auto Xoff flow control */
ier &= ~UART_17158_IER_XOFF;
if (ch->ch_c_iflag & IXON)
efr &= ~(UART_17158_EFR_IXOFF);
else
efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
/* Why? Becuz Exar's spec says we have to zero it out before setting it */
writeb(0, &ch->ch_neo_uart->efr);
/* Turn on UART enhanced bits */
writeb(efr, &ch->ch_neo_uart->efr);
/* Turn on table D, with 8 char hi/low watermarks */
writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
ch->ch_r_watermark = 0;
writeb(16, &ch->ch_neo_uart->tfifo);
ch->ch_t_tlevel = 16;
writeb(16, &ch->ch_neo_uart->rfifo);
ch->ch_r_tlevel = 16;
writeb(ier, &ch->ch_neo_uart->ier);
neo_pci_posting_flush(ch->ch_bd);
}
