/* EU takes the value from the flag register and pushes it onto some
* sort of a stack (presumably merging with any flag value already on
* the stack). Within an if block, the flags at the top of the stack
* control execution on each channel of the unit, eg. on each of the
* 16 pixel values in our wm programs.
*
* When the matching 'else' instruction is reached (presumably by
* countdown of the instruction count patched in by our ELSE/ENDIF
* functions), the relevent flags are inverted.
*
* When the matching 'endif' instruction is reached, the flags are
* popped off. If the stack is now empty, normal execution resumes.
*
* No attempt is made to deal with stack overflow (14 elements?).
*/
struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
{
struct brw_instruction *insn;
if (p->single_program_flow) {
assert(execute_size == BRW_EXECUTE_1);
insn = next_insn(p, BRW_OPCODE_ADD);
insn->header.predicate_inverse = 1;
} else {
insn = next_insn(p, BRW_OPCODE_IF);
}
/* Override the defaults for this instruction:
*/
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.execution_size = execute_size;
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.predicate_control = BRW_PREDICATE_NORMAL;
insn->header.mask_control = BRW_MASK_ENABLE;
if (!p->single_program_flow)
insn->header.thread_control = BRW_THREAD_SWITCH;
p->current->header.predicate_control = BRW_PREDICATE_NONE;
return insn;
}
struct brw_instruction *brw_WHILE(struct brw_compile *p,
struct brw_instruction *do_insn)
{
struct brw_instruction *insn;
if (p->single_program_flow)
insn = next_insn(p, BRW_OPCODE_ADD);
else
insn = next_insn(p, BRW_OPCODE_WHILE);
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
if (p->single_program_flow) {
insn->header.execution_size = BRW_EXECUTE_1;
insn->bits3.d = (do_insn - insn) * 16;
} else {
insn->header.execution_size = do_insn->header.execution_size;
assert(do_insn->header.opcode == BRW_OPCODE_DO);
insn->bits3.if_else.jump_count = do_insn - insn + 1;
insn->bits3.if_else.pop_count = 0;
insn->bits3.if_else.pad0 = 0;
}
/* insn->header.mask_control = BRW_MASK_ENABLE; */
/* insn->header.mask_control = BRW_MASK_DISABLE; */
p->current->header.predicate_control = BRW_PREDICATE_NONE;
return insn;
}
/**
* Extended math function, float[16].
* Use 2 send instructions.
*/
void brw_math_16( struct brw_compile *p,
struct brw_reg dest,
GLuint function,
GLuint saturate,
GLuint msg_reg_nr,
struct brw_reg src,
GLuint precision )
{
struct brw_instruction *insn;
GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1;
GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1;
/* First instruction:
*/
brw_push_insn_state(p);
brw_set_predicate_control_flag_value(p, 0xff);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(insn, dest);
brw_set_src0(insn, src);
brw_set_math_message(p->brw,
insn,
msg_length, response_length,
function,
BRW_MATH_INTEGER_UNSIGNED,
precision,
saturate,
BRW_MATH_DATA_VECTOR);
/* Second instruction:
*/
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.compression_control = BRW_COMPRESSION_2NDHALF;
insn->header.destreg__conditionalmod = msg_reg_nr+1;
brw_set_dest(insn, offset(dest,1));
brw_set_src0(insn, src);
brw_set_math_message(p->brw,
insn,
msg_length, response_length,
function,
BRW_MATH_INTEGER_UNSIGNED,
precision,
saturate,
BRW_MATH_DATA_VECTOR);
brw_pop_insn_state(p);
}
void brw_NOP(struct brw_compile *p)
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(insn, brw_imm_ud(0x0));
}
/** Extended math function, float[8].
*/
void brw_math( struct brw_compile *p,
struct brw_reg dest,
GLuint function,
GLuint saturate,
GLuint msg_reg_nr,
struct brw_reg src,
GLuint data_type,
GLuint precision )
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1;
GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1;
/* Example code doesn't set predicate_control for send
* instructions.
*/
insn->header.predicate_control = 0;
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(insn, dest);
brw_set_src0(insn, src);
brw_set_math_message(p->brw,
insn,
msg_length, response_length,
function,
BRW_MATH_INTEGER_UNSIGNED,
precision,
saturate,
data_type);
}
void brw_ff_sync(struct brw_compile *p,
struct brw_reg dest,
GLuint msg_reg_nr,
struct brw_reg src0,
GLboolean allocate,
GLboolean used,
GLuint msg_length,
GLuint response_length,
GLboolean eot,
GLboolean writes_complete,
GLuint offset,
GLuint swizzle)
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
assert(msg_length < 16);
brw_set_dest(insn, dest);
brw_set_src0(insn, src0);
brw_set_src1(insn, brw_imm_d(0));
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_ff_sync_message(p->brw,
insn,
allocate,
used,
msg_length,
response_length,
eot,
writes_complete,
offset,
swizzle);
}
/* To integrate with the above, it makes sense that the comparison
* instruction should populate the flag register. It might be simpler
* just to use the flag reg for most WM tasks?
*/
void brw_CMP(struct brw_compile *p,
struct brw_reg dest,
GLuint conditional,
struct brw_reg src0,
struct brw_reg src1)
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
insn->header.destreg__conditionalmod = conditional;
brw_set_dest(insn, dest);
brw_set_src0(insn, src0);
brw_set_src1(insn, src1);
/* guess_execution_size(insn, src0); */
/* Make it so that future instructions will use the computed flag
* value until brw_set_predicate_control_flag_value() is called
* again.
*/
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == 0) {
p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
p->flag_value = 0xff;
}
}
void brw_fb_WRITE(struct brw_compile *p,
struct brw_reg dest,
GLuint msg_reg_nr,
struct brw_reg src0,
GLuint binding_table_index,
GLuint msg_length,
GLuint response_length,
GLboolean eot)
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(insn, dest);
brw_set_src0(insn, src0);
brw_set_dp_write_message(p->brw,
insn,
binding_table_index,
BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE, /* msg_control */
BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE, /* msg_type */
msg_length,
1, /* pixel scoreboard */
response_length,
eot);
}
void brw_ENDIF(struct brw_compile *p,
struct brw_instruction *patch_insn)
{
GLuint br = 1;
if (BRW_IS_IGDNG(p->brw))
br = 2;
if (p->single_program_flow) {
/* In single program flow mode, there's no need to execute an ENDIF,
* since we don't need to do any stack operations, and if we're executing
* currently, we want to just continue executing.
*/
struct brw_instruction *next = &p->store[p->nr_insn];
assert(patch_insn->header.opcode == BRW_OPCODE_ADD);
patch_insn->bits3.ud = (next - patch_insn) * 16;
} else {
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = patch_insn->header.execution_size;
insn->header.mask_control = BRW_MASK_ENABLE;
insn->header.thread_control = BRW_THREAD_SWITCH;
assert(patch_insn->bits3.if_else.jump_count == 0);
/* Patch the if or else instructions to point at this or the next
* instruction respectively.
*/
if (patch_insn->header.opcode == BRW_OPCODE_IF) {
/* Automagically turn it into an IFF:
*/
patch_insn->header.opcode = BRW_OPCODE_IFF;
patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1);
patch_insn->bits3.if_else.pop_count = 0;
patch_insn->bits3.if_else.pad0 = 0;
} else if (patch_insn->header.opcode == BRW_OPCODE_ELSE) {
patch_insn->bits3.if_else.jump_count = br * (insn - patch_insn + 1);
patch_insn->bits3.if_else.pop_count = 1;
patch_insn->bits3.if_else.pad0 = 0;
} else {
assert(0);
}
/* Also pop item off the stack in the endif instruction:
*/
insn->bits3.if_else.jump_count = 0;
insn->bits3.if_else.pop_count = 1;
insn->bits3.if_else.pad0 = 0;
}
}
static struct brw_instruction *brw_alu1( struct brw_compile *p,
GLuint opcode,
struct brw_reg dest,
struct brw_reg src )
{
struct brw_instruction *insn = next_insn(p, opcode);
brw_set_dest(insn, dest);
brw_set_src0(insn, src);
return insn;
}
struct brw_instruction *brw_ELSE(struct brw_compile *p,
struct brw_instruction *if_insn)
{
struct brw_instruction *insn;
GLuint br = 1;
if (BRW_IS_IGDNG(p->brw))
br = 2;
if (p->single_program_flow) {
insn = next_insn(p, BRW_OPCODE_ADD);
} else {
insn = next_insn(p, BRW_OPCODE_ELSE);
}
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = if_insn->header.execution_size;
insn->header.mask_control = BRW_MASK_ENABLE;
if (!p->single_program_flow)
insn->header.thread_control = BRW_THREAD_SWITCH;
/* Patch the if instruction to point at this instruction.
*/
if (p->single_program_flow) {
assert(if_insn->header.opcode == BRW_OPCODE_ADD);
if_insn->bits3.ud = (insn - if_insn + 1) * 16;
} else {
assert(if_insn->header.opcode == BRW_OPCODE_IF);
if_insn->bits3.if_else.jump_count = br * (insn - if_insn);
if_insn->bits3.if_else.pop_count = 0;
if_insn->bits3.if_else.pad0 = 0;
}
return insn;
}
struct brw_instruction *brw_CONT(struct brw_compile *p)
{
struct brw_instruction *insn;
insn = next_insn(p, BRW_OPCODE_CONTINUE);
brw_set_dest(insn, brw_ip_reg());
brw_set_src0(insn, brw_ip_reg());
brw_set_src1(insn, brw_imm_d(0x0));
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = BRW_EXECUTE_8;
/* insn->header.mask_control = BRW_MASK_DISABLE; */
insn->bits3.if_else.pad0 = 0;
return insn;
}
/**
* Read a float[4] vector from the data port Data Cache (const buffer).
* Location (in buffer) should be a multiple of 16.
* Used for fetching shader constants.
* If relAddr is true, we'll do an indirect fetch using the address register.
*/
void brw_dp_READ_4( struct brw_compile *p,
struct brw_reg dest,
GLboolean relAddr,
GLuint location,
GLuint bind_table_index )
{
/* XXX: relAddr not implemented */
GLuint msg_reg_nr = 1;
{
struct brw_reg b;
brw_push_insn_state(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
/* Setup MRF[1] with location/offset into const buffer */
b = brw_message_reg(msg_reg_nr);
b = retype(b, BRW_REGISTER_TYPE_UD);
/* XXX I think we're setting all the dwords of MRF[1] to 'location'.
* when the docs say only dword[2] should be set. Hmmm. But it works.
*/
brw_MOV(p, b, brw_imm_ud(location));
brw_pop_insn_state(p);
}
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = BRW_PREDICATE_NONE;
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.destreg__conditionalmod = msg_reg_nr;
insn->header.mask_control = BRW_MASK_DISABLE;
/* cast dest to a uword[8] vector */
dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
brw_set_dest(insn, dest);
brw_set_src0(insn, brw_null_reg());
brw_set_dp_read_message(p->brw,
insn,
bind_table_index,
0, /* msg_control (0 means 1 Oword) */
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */
0, /* source cache = data cache */
1, /* msg_length */
1, /* response_length (1 Oword) */
0); /* eot */
}
}
/**
* Write block of 16 dwords/floats to the data port Render Cache scratch buffer.
* Scratch offset should be a multiple of 64.
* Used for register spilling.
*/
void brw_dp_WRITE_16( struct brw_compile *p,
struct brw_reg src,
GLuint scratch_offset )
{
GLuint msg_reg_nr = 1;
{
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
/* set message header global offset field (reg 0, element 2) */
brw_MOV(p,
retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D),
brw_imm_d(scratch_offset));
brw_pop_insn_state(p);
}
{
GLuint msg_length = 3;
struct brw_reg dest = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(insn, dest);
brw_set_src0(insn, src);
brw_set_dp_write_message(p->brw,
insn,
255, /* binding table index (255=stateless) */
BRW_DATAPORT_OWORD_BLOCK_4_OWORDS, /* msg_control */
BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, /* msg_type */
msg_length,
0, /* pixel scoreboard */
0, /* response_length */
0); /* eot */
}
}
/* DO/WHILE loop:
*/
struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
{
if (p->single_program_flow) {
return &p->store[p->nr_insn];
} else {
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
/* Override the defaults for this instruction:
*/
brw_set_dest(insn, brw_null_reg());
brw_set_src0(insn, brw_null_reg());
brw_set_src1(insn, brw_null_reg());
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.execution_size = execute_size;
insn->header.predicate_control = BRW_PREDICATE_NONE;
/* insn->header.mask_control = BRW_MASK_ENABLE; */
/* insn->header.mask_control = BRW_MASK_DISABLE; */
return insn;
}
}
/**
* Read block of 16 dwords/floats from the data port Render Cache scratch buffer.
* Scratch offset should be a multiple of 64.
* Used for register spilling.
*/
void brw_dp_READ_16( struct brw_compile *p,
struct brw_reg dest,
GLuint scratch_offset )
{
GLuint msg_reg_nr = 1;
{
brw_push_insn_state(p);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
/* set message header global offset field (reg 0, element 2) */
brw_MOV(p,
retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D),
brw_imm_d(scratch_offset));
brw_pop_insn_state(p);
}
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(insn, dest); /* UW? */
brw_set_src0(insn, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW));
brw_set_dp_read_message(p->brw,
insn,
255, /* binding table index (255=stateless) */
3, /* msg_control (3 means 4 Owords) */
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */
1, /* target cache (render/scratch) */
1, /* msg_length */
2, /* response_length */
0); /* eot */
}
}
// Create a function frame
bool idaapi create_func_frame(func_t *pfn) {
ushort savedreg_size = 0;
uint32 args_size = 0;
uint32 localvar_size;
ea_t ea = pfn->startEA;
// detect multiple ``st Ri, @-R15'' instructions.
while ( (ea = next_insn(ea) ) != 0 &&
cmd.itype == fr_st &&
cmd.Op1.type == o_reg &&
cmd.Op2.type == o_phrase &&
cmd.Op2.reg == rR15 &&
cmd.Op2.specflag2 == fIGRM)
{
savedreg_size += 4;
#if defined(__DEBUG__)
msg("0x%a: detected st Rx, @-R15\n", ea);
#endif /* __DEBUG__ */
}
// detect enter #nn
if ( cmd.itype == fr_enter ) {
// R14 is automatically pushed by fr_enter
savedreg_size += 4;
localvar_size = uint32(cmd.Op1.value - 4);
#if defined(__DEBUG__)
msg("0x%a: detected enter #0x%a\n", ea, cmd.Op1.value);
#endif /* __DEBUG__ */
}
// detect mov R15, R14 + ldi #imm, R0 instructions
else {
if (cmd.itype != fr_mov ||
cmd.Op1.type != o_reg ||
cmd.Op1.reg != rR15 ||
cmd.Op2.type != o_reg ||
cmd.Op2.reg != rR14)
{
goto bad_func;
}
/*ea = */next_insn(ea);
if ( (cmd.itype == fr_ldi_20 || cmd.itype == fr_ldi_32 ) &&
cmd.Op1.type == o_imm &&
cmd.Op2.type == o_reg &&
cmd.Op2.reg == rR0)
{
localvar_size = uint32(cmd.Op1.value);
}
else
goto bad_func;
#if defined(__DEBUG__)
msg("0x%a: detected ldi #0x%a, R0\n", ea, cmd.Op1.value);
#endif /* __DEBUG__ */
}
// XXX we don't care about near/far functions, because currently
// we don't know how to detect them ;-)
pfn->flags |= FUNC_FRAME;
return add_frame(pfn, localvar_size, savedreg_size, args_size);
bad_func:
return 0;
}
// Emulate an operand.
static void handle_operand(op_t &op) {
bool offset = false;
switch ( op.type ) {
case o_near:
ua_add_cref(op.offb, toEA(cmd.cs, op.addr), (cmd.itype == fr_call) ? fl_CN : fl_JN);
break;
case o_mem:
{
enum dref_t mode = dr_U;
if ( op.specflag1 & OP_ADDR_R ) mode = dr_R;
else if ( op.specflag1 & OP_ADDR_W ) mode = dr_W;
ea_t ea = toEA(cmd.cs, op.addr);
ua_add_dref(op.offb, ea, mode);
ua_dodata2(op.offb, ea, op.dtyp);
}
break;
case o_imm:
// if current insn is ldi:32 #imm, r1
// and next insn is call @r1,
// replace the immediate value with an offset.
if (cmd.itype == fr_ldi_32 &&
cmd.Op1.type == o_imm &&
cmd.Op2.type == o_reg)
{
const int callreg = cmd.Op2.reg;
insn_t cmd_backup = cmd;
if ( next_insn(cmd.ea + cmd.size ) > 0 &&
cmd.itype == fr_call &&
cmd.Op1.type == o_phrase &&
cmd.Op1.specflag2 == fIGR &&
cmd.Op1.reg == callreg)
{
offset = true;
}
const ea_t from = cmd.ea;
cmd = cmd_backup;
if ( !isDefArg(uFlag, 0) && offset && set_offset(cmd.ea, 0, 0) )
add_cref(from, toEA(cmd.cs, cmd.Op1.value), fl_CN);
}
doImmd(cmd.ea);
if ( !offset )
// if the value was converted to an offset, then create a data xref:
if ( isOff(uFlag, op.n) )
ua_add_off_drefs2(op, dr_O, 0);
// create stack variables if necessary
{
bool ok = false;
// ldi8 #our_value, R1
// extsb R1
// addn R14, R1
if (cmd.itype == fr_ldi_8 &&
cmd.Op2.type == o_reg &&
cmd.Op2.reg == rR1)
{
insn_t current_insn = cmd;
next_insn(cmd.ea + cmd.size);
if (cmd.itype == fr_extsb &&
cmd.Op1.type == o_reg &&
cmd.Op1.reg == rR1)
{
ok = true;
}
if ( ok ) {
ok = false;
next_insn(cmd.ea + cmd.size);
if (cmd.itype == fr_addn &&
cmd.Op1.type == o_reg &&
cmd.Op1.reg == rR14 &&
cmd.Op2.type == o_reg &&
cmd.Op2.reg == rR1)
{
ok = true;
}
}
cmd = current_insn;
}
// ldi32 #our_value, Ri
// addn R14, Ri
//
// (where Ri is either R1 or R2)
else if (cmd.itype == fr_ldi_32 &&
cmd.Op2.type == o_reg &&
(cmd.Op2.reg == rR1 || cmd.Op2.reg == rR2))
{
ushort the_reg = cmd.Op2.reg;
insn_t current_insn = cmd;
next_insn(cmd.ea + cmd.size);
if (cmd.itype == fr_addn &&
cmd.Op1.type == o_reg &&
cmd.Op1.reg == rR14 &&
cmd.Op2.type == o_reg &&
cmd.Op2.reg == the_reg)
{
ok = true;
}
cmd = current_insn;
}
if ( ok && may_create_stkvars() && !isDefArg(uFlag, op.n) ) {
func_t *pfn = get_func(cmd.ea);
if ( pfn != NULL && pfn->flags & FUNC_FRAME ) {
if ( ua_stkvar2(op, op.value, 0) ) {
op_stkvar(cmd.ea, op.n);
}
}
}
}
break;
case o_displ:
case o_phrase: // XXX
case o_reglist:
case o_void:
case o_reg:
break;
default:
INTERR(10017);
}
}
/**
* Texture sample instruction.
* Note: the msg_type plus msg_length values determine exactly what kind
* of sampling operation is performed. See volume 4, page 161 of docs.
*/
void brw_SAMPLE(struct brw_compile *p,
struct brw_reg dest,
GLuint msg_reg_nr,
struct brw_reg src0,
GLuint binding_table_index,
GLuint sampler,
GLuint writemask,
GLuint msg_type,
GLuint response_length,
GLuint msg_length,
GLboolean eot,
GLuint header_present,
GLuint simd_mode)
{
GLboolean need_stall = 0;
if (writemask == 0) {
/*_mesa_printf("%s: zero writemask??\n", __FUNCTION__); */
return;
}
/* Hardware doesn't do destination dependency checking on send
* instructions properly. Add a workaround which generates the
* dependency by other means. In practice it seems like this bug
* only crops up for texture samples, and only where registers are
* written by the send and then written again later without being
* read in between. Luckily for us, we already track that
* information and use it to modify the writemask for the
* instruction, so that is a guide for whether a workaround is
* needed.
*/
if (writemask != WRITEMASK_XYZW) {
GLuint dst_offset = 0;
GLuint i, newmask = 0, len = 0;
for (i = 0; i < 4; i++) {
if (writemask & (1<<i))
break;
dst_offset += 2;
}
for (; i < 4; i++) {
if (!(writemask & (1<<i)))
break;
newmask |= 1<<i;
len++;
}
if (newmask != writemask) {
need_stall = 1;
/* _mesa_printf("need stall %x %x\n", newmask , writemask); */
}
else {
struct brw_reg m1 = brw_message_reg(msg_reg_nr);
newmask = ~newmask & WRITEMASK_XYZW;
brw_push_insn_state(p);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, m1, brw_vec8_grf(0,0));
brw_MOV(p, get_element_ud(m1, 2), brw_imm_ud(newmask << 12));
brw_pop_insn_state(p);
src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW);
dest = offset(dest, dst_offset);
response_length = len * 2;
}
}
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.destreg__conditionalmod = msg_reg_nr;
brw_set_dest(insn, dest);
brw_set_src0(insn, src0);
brw_set_sampler_message(p->brw, insn,
binding_table_index,
sampler,
msg_type,
response_length,
msg_length,
eot,
header_present,
simd_mode);
}
if (need_stall) {
struct brw_reg reg = vec8(offset(dest, response_length-1));
/* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 }
*/
brw_push_insn_state(p);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_MOV(p, reg, reg);
brw_pop_insn_state(p);
}
}
/**
* Read float[4] constant(s) from VS constant buffer.
* For relative addressing, two float[4] constants will be read into 'dest'.
* Otherwise, one float[4] constant will be read into the lower half of 'dest'.
*/
void brw_dp_READ_4_vs(struct brw_compile *p,
struct brw_reg dest,
GLuint oword,
GLboolean relAddr,
struct brw_reg addrReg,
GLuint location,
GLuint bind_table_index)
{
GLuint msg_reg_nr = 1;
assert(oword < 2);
/*
printf("vs const read msg, location %u, msg_reg_nr %d\n",
location, msg_reg_nr);
*/
/* Setup MRF[1] with location/offset into const buffer */
{
struct brw_reg b;
brw_push_insn_state(p);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
/*brw_set_access_mode(p, BRW_ALIGN_16);*/
/* XXX I think we're setting all the dwords of MRF[1] to 'location'.
* when the docs say only dword[2] should be set. Hmmm. But it works.
*/
b = brw_message_reg(msg_reg_nr);
b = retype(b, BRW_REGISTER_TYPE_UD);
/*b = get_element_ud(b, 2);*/
if (relAddr) {
brw_ADD(p, b, addrReg, brw_imm_ud(location));
}
else {
brw_MOV(p, b, brw_imm_ud(location));
}
brw_pop_insn_state(p);
}
{
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = BRW_PREDICATE_NONE;
insn->header.compression_control = BRW_COMPRESSION_NONE;
insn->header.destreg__conditionalmod = msg_reg_nr;
insn->header.mask_control = BRW_MASK_DISABLE;
/*insn->header.access_mode = BRW_ALIGN_16;*/
brw_set_dest(insn, dest);
brw_set_src0(insn, brw_null_reg());
brw_set_dp_read_message(p->brw,
insn,
bind_table_index,
oword, /* 0 = lower Oword, 1 = upper Oword */
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */
0, /* source cache = data cache */
1, /* msg_length */
1, /* response_length (1 Oword) */
0); /* eot */
}
}
