static int ninja32_reinit_one(struct pci_dev *pdev) { struct ata_host *host = dev_get_drvdata(&pdev->dev); int rc; rc = ata_pci_device_do_resume(pdev); if (rc) return rc; ninja32_program(host->iomap[0]); ata_host_resume(host); <<<<<<< HEAD
static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) { struct ata_host *host; struct ata_port *ap; void __iomem *base; int rc; host = ata_host_alloc(&dev->dev, 1); if (!host) return -ENOMEM; ap = host->ports[0]; /* Set up the PCI device */ rc = pcim_enable_device(dev); if (rc) return rc; rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME); if (rc == -EBUSY) pcim_pin_device(dev); if (rc) return rc; host->iomap = pcim_iomap_table(dev); rc = pci_set_dma_mask(dev, ATA_DMA_MASK); if (rc) return rc; rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK); if (rc) return rc; pci_set_master(dev); /* Set up the register mappings. We use the I/O mapping as only the older chips also have MMIO on BAR 1 */ base = host->iomap[0]; if (!base) return -ENOMEM; ap->ops = &ninja32_port_ops; ap->pio_mask = ATA_PIO4; ap->flags |= ATA_FLAG_SLAVE_POSS; ap->ioaddr.cmd_addr = base + 0x10; ap->ioaddr.ctl_addr = base + 0x1E; ap->ioaddr.altstatus_addr = base + 0x1E; ap->ioaddr.bmdma_addr = base; ata_sff_std_ports(&ap->ioaddr); ap->pflags = ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; ninja32_program(base); /* FIXME: Should we disable them at remove ? */ return ata_host_activate(host, dev->irq, ata_bmdma_interrupt, IRQF_SHARED, &ninja32_sht); }
static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) { struct ata_host *host; struct ata_port *ap; void __iomem *base; int rc; host = ata_host_alloc(&dev->dev, 1); if (!host) return -ENOMEM; ap = host->ports[0]; rc = pcim_enable_device(dev); if (rc) return rc; rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME); if (rc == -EBUSY) pcim_pin_device(dev); if (rc) return rc; host->iomap = pcim_iomap_table(dev); rc = pci_set_dma_mask(dev, ATA_DMA_MASK); if (rc) return rc; rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK); if (rc) return rc; pci_set_master(dev); base = host->iomap[0]; if (!base) return -ENOMEM; ap->ops = &ninja32_port_ops; ap->pio_mask = ATA_PIO4; ap->flags |= ATA_FLAG_SLAVE_POSS; ap->ioaddr.cmd_addr = base + 0x10; ap->ioaddr.ctl_addr = base + 0x1E; ap->ioaddr.altstatus_addr = base + 0x1E; ap->ioaddr.bmdma_addr = base; ata_sff_std_ports(&ap->ioaddr); ap->pflags = ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; ninja32_program(base); return ata_host_activate(host, dev->irq, ata_sff_interrupt, IRQF_SHARED, &ninja32_sht); }